1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"DC error reduction in bipolar opamps","authors":"R. Widlar","doi":"10.1109/ISSCC.1980.1156040","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156040","url":null,"abstract":"A bipolar opamp design providing 100μV offset voltage, 1μV/°C drift and 20pA bias current will be described. In contrast to FETs, performance is maintained to 125°C.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"X-series approach to high density 128K and high speed 32K EPROMs","authors":"D. Guterman, J. Klaas, G. Armstrong, J. Neal, D. McElroy, P. Reed, W. Richardson, H. Stiegler, I. Rimawi","doi":"10.1109/ISSCC.1980.1156100","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156100","url":null,"abstract":"PRESENT GENERATION EPROMs have several serious limitations which restrict them to devices of low speed and moderate size'. To improve significantly EPROM density and performance, the present barriers, which include low FAMOS drive capabilities and relatively large cell configurations, have been addressed in this effort through a multipronged attack; the Xscries approach. The cell array has been reconfigured which, in combination with scaling, offers a memory of significantly higher density. The FAMOS performance has been improved through scaling and process innovation, resulting in higher cell drive without significant reduction in programmability. Circuit approaches taking advantage of updated memory architecture and performance to provide higher EPROM speeds have been adopted.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125295764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power combining near 94GHz","authors":"Kai Chang, R. Ebert","doi":"10.1109/ISSCC.1980.1156058","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156058","url":null,"abstract":"Power combiners using double-drift IMPATT diodes developed to generate peak output power of 20.5W from two diodes and 40W from four diodes at frequencies near 94GHz with over 80% combining efficiency, will be discussed.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123375597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 64K EPROM using scaled MOS technology","authors":"G. Perlegos, S. Pathak, A. Renninger, W. Johnson, M. Holler, J. Skupnak, M. Reitsma, G. Kuhn","doi":"10.1109/ISSCC.1980.1156041","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156041","url":null,"abstract":"This paper will report on a 64Kb static MOS EPROM which combines a two-layer poly self-aligned memory cell together with scaled NMOS periphery technology. Cell size is 0.24μm2/b. Access time is 200ns.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130831560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 256K RAM fabricated with molybdenum-polysilicon technology","authors":"T. Mano, K. Takeya, T. Watanabe, K. Kiuchi, T. Ogawa, K. Hirata","doi":"10.1109/ISSCC.1980.1156098","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156098","url":null,"abstract":"128K block has two arrays of 64Kb fundamental cells and about 2Kb spare cells, and dummy sense circuit’. The spare cells are connected with four pairs of spare bit-lines and two spare word-lines. Since each pair of spare bit-lines require one additional sense amplifier, one block bas 516 amplifiers. The amplifier includes coupling capacitors, which make it possible to obtain a high refresh voltage. Amplifier circuits and operating waveforms are shown in Figure 2. The amplifier begins to detect the signal by clock @ ~ 1 , and amplification is accelerated by clock @ ~ 2 . After sensing operation the capacitors are connected with the bit-lines by clock @B. Therefore the potential of the bit-line becomes high enough for refreshing. Clock @ ~ 1 also drives the coupling capacitors. During sensing period, however, the capacitors are separated from the bitlines to prevent an increase in bit-line capacitance. As a result, this amplifier can detect a signal of ? 50mV. In the memory cell array the word line crosses over the storage capacitor electrodes, and is composed of molybdenum, which is the gate material of the cell transistor2. The bit-line is made of interconnection metal of aluminum and the storage capacitor electrode consists of polysilicon. The memory cell has been designed to obtain the signal of * 120mV in the worst case. Since both the word-line and bit-line materials are metallic, the propagation delay in the array becomes small. In other circuits Si-gate transistors are used. To improve the yield of RAMS the fault-tolerant concept is introduced. Spare cells can substitute for defective cells. This substitution is achieved by utilizing electrically programmable polysilieon resistors, which include PN junctions. Figure 3 shows the spare column decoder using these resistors. The resistance is at least 109Q initially, and it becomes less than 3 x l O 3 Q after transition. Since the resistor has low transition voltage and current (11V and 7mA), programming is controlled easily by MOS circuits. The substitution requires only 15V programming pulses and can be done during wafer probing. The resistor characteristic is shown in Figure 4. To program the A block diagram of the circuit is shown in Figure 1. Each","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134276801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Competing technologies for Gb logic","authors":"L. Nevin","doi":"10.1109/ISSCC.1980.1156025","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156025","url":null,"abstract":"Global Gb logic developments involve major technology approaches in GaAs ICs, silicon ICs and Josephson junctions. With major performance advances occurring rapidly in each area, it is important to maintain objective comparisons of the technologies. Valid comparisons require evaluation against extended objectives which include not only power-delay products, but also other measures of total performance including interfacing capabilities, design flexibility, technology investment requirements, product reliability and manufacturability. These objectives will be the context in which recent Gb logic achievements will be surveyed and compared.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129274667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A linear compatible I2L servo LSI for video recording","authors":"T. Nakamura, K. Nakano, S. Ido, M. Mizunoue, K. Asano","doi":"10.1109/ISSCC.1980.1156039","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156039","url":null,"abstract":"This paper will describe an LSI with 3000 I2L gates and 350 linear element, monolithically combined for servo control of VTRs. The circuit includes PWM-type D/A conversion and steady-state error compensation with interface circuitry for playback speed control and editing point adjustment.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124362671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 8-channel data acquisition system with DMA","authors":"D. Burton, H. Krabbe, H. Tucholski","doi":"10.1109/ISSCC.1980.1156102","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156102","url":null,"abstract":"An 8-channel, 8b CMOS data acquisition system which includes an 8-word dual-port memory and DMA control on chip, will be reported. The memory provides an A/D process totally transparent to microcomputers.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124284414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully static 16Kb bulk CMOS RAM","authors":"T. Iizuka, K. Ochii, T. Ohtani, T. Kondo, S. Koyhama","doi":"10.1109/ISSCC.1980.1156077","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156077","url":null,"abstract":"A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 400ps bipolar 18b RALU","authors":"F. Sato, S. Wakamatsu, T. Kubota, K. Kimura","doi":"10.1109/ISSCC.1980.1156145","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156145","url":null,"abstract":"An 18b VLSI bipolar (0.4ns/2.5mW) RALU with 1300 gates and a 7ns read-modify-write cycle will be reported. Using four chips, a 72b ALU can be operated at 100MHz.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123890767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}