全静态16Kb大块CMOS RAM

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156077

T. Iizuka, K. Ochii, T. Ohtani, T. Kondo, S. Koyhama

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引用次数: 10

摘要

将介绍用于设计具有6晶体管单元的全静态16Kb大块CMOS RAM的共面si栅极CMOS工艺。RAM的典型访问时间为95ns，功耗为200mW，待机功率为1μW。

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Fully static 16Kb bulk CMOS RAM

A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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