采用钼-多晶硅技术制造的256K RAM

T. Mano, K. Takeya, T. Watanabe, K. Kiuchi, T. Ogawa, K. Hirata
{"title":"采用钼-多晶硅技术制造的256K RAM","authors":"T. Mano, K. Takeya, T. Watanabe, K. Kiuchi, T. Ogawa, K. Hirata","doi":"10.1109/ISSCC.1980.1156098","DOIUrl":null,"url":null,"abstract":"128K block has two arrays of 64Kb fundamental cells and about 2Kb spare cells, and dummy sense circuit’. The spare cells are connected with four pairs of spare bit-lines and two spare word-lines. Since each pair of spare bit-lines require one additional sense amplifier, one block bas 516 amplifiers. The amplifier includes coupling capacitors, which make it possible to obtain a high refresh voltage. Amplifier circuits and operating waveforms are shown in Figure 2. The amplifier begins to detect the signal by clock @ ~ 1 , and amplification is accelerated by clock @ ~ 2 . After sensing operation the capacitors are connected with the bit-lines by clock @B. Therefore the potential of the bit-line becomes high enough for refreshing. Clock @ ~ 1 also drives the coupling capacitors. During sensing period, however, the capacitors are separated from the bitlines to prevent an increase in bit-line capacitance. As a result, this amplifier can detect a signal of ? 50mV. In the memory cell array the word line crosses over the storage capacitor electrodes, and is composed of molybdenum, which is the gate material of the cell transistor2. The bit-line is made of interconnection metal of aluminum and the storage capacitor electrode consists of polysilicon. The memory cell has been designed to obtain the signal of * 120mV in the worst case. Since both the word-line and bit-line materials are metallic, the propagation delay in the array becomes small. In other circuits Si-gate transistors are used. To improve the yield of RAMS the fault-tolerant concept is introduced. Spare cells can substitute for defective cells. This substitution is achieved by utilizing electrically programmable polysilieon resistors, which include PN junctions. Figure 3 shows the spare column decoder using these resistors. The resistance is at least 109Q initially, and it becomes less than 3 x l O 3 Q after transition. Since the resistor has low transition voltage and current (11V and 7mA), programming is controlled easily by MOS circuits. The substitution requires only 15V programming pulses and can be done during wafer probing. The resistor characteristic is shown in Figure 4. To program the A block diagram of the circuit is shown in Figure 1. Each","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"183 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"A 256K RAM fabricated with molybdenum-polysilicon technology\",\"authors\":\"T. Mano, K. Takeya, T. Watanabe, K. Kiuchi, T. Ogawa, K. Hirata\",\"doi\":\"10.1109/ISSCC.1980.1156098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"128K block has two arrays of 64Kb fundamental cells and about 2Kb spare cells, and dummy sense circuit’. The spare cells are connected with four pairs of spare bit-lines and two spare word-lines. Since each pair of spare bit-lines require one additional sense amplifier, one block bas 516 amplifiers. The amplifier includes coupling capacitors, which make it possible to obtain a high refresh voltage. Amplifier circuits and operating waveforms are shown in Figure 2. The amplifier begins to detect the signal by clock @ ~ 1 , and amplification is accelerated by clock @ ~ 2 . After sensing operation the capacitors are connected with the bit-lines by clock @B. Therefore the potential of the bit-line becomes high enough for refreshing. Clock @ ~ 1 also drives the coupling capacitors. During sensing period, however, the capacitors are separated from the bitlines to prevent an increase in bit-line capacitance. As a result, this amplifier can detect a signal of ? 50mV. In the memory cell array the word line crosses over the storage capacitor electrodes, and is composed of molybdenum, which is the gate material of the cell transistor2. The bit-line is made of interconnection metal of aluminum and the storage capacitor electrode consists of polysilicon. The memory cell has been designed to obtain the signal of * 120mV in the worst case. Since both the word-line and bit-line materials are metallic, the propagation delay in the array becomes small. In other circuits Si-gate transistors are used. To improve the yield of RAMS the fault-tolerant concept is introduced. Spare cells can substitute for defective cells. This substitution is achieved by utilizing electrically programmable polysilieon resistors, which include PN junctions. Figure 3 shows the spare column decoder using these resistors. The resistance is at least 109Q initially, and it becomes less than 3 x l O 3 Q after transition. Since the resistor has low transition voltage and current (11V and 7mA), programming is controlled easily by MOS circuits. The substitution requires only 15V programming pulses and can be done during wafer probing. The resistor characteristic is shown in Figure 4. To program the A block diagram of the circuit is shown in Figure 1. Each\",\"PeriodicalId\":229101,\"journal\":{\"name\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"183 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1980.1156098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28

摘要

128K块有两个64Kb的基本单元和约2Kb的备用单元阵列,以及虚拟感测电路。备用单元通过4对备用位线和2对备用字线连接。由于每对备用位线需要一个额外的感测放大器,一个块有516个放大器。放大器包括耦合电容器,这使得获得高刷新电压成为可能。放大电路和工作波形如图2所示。放大器通过时钟@ ~ 1开始检测信号,并通过时钟@ ~ 2加速放大。感应操作后,电容器通过时钟@B与位线连接。因此,位线的潜力变得足够高,可以进行刷新。时钟@ ~ 1也驱动耦合电容器。然而,在感应期间,电容器与位线分开,以防止位线电容的增加。因此,该放大器可以检测到的信号为?50 mv。在存储单元阵列中,字线横跨存储电容器电极,由钼组成,钼是存储单元晶体管的栅极材料2。位线由互连金属铝构成,存储电容器电极由多晶硅构成。设计的存储单元可以在最坏的情况下获得* 120mV的信号。由于字线和位线材料都是金属材料,因此阵列中的传播延迟变得很小。在其他电路中使用硅栅晶体管。为了提高ram的成品率,引入了容错的概念。备用细胞可以代替有缺陷的细胞。这种替代是通过利用电可编程多晶硅电阻实现的,其中包括PN结。图3显示了使用这些电阻的备用列解码器。初始电阻至少为109Q,过渡后电阻小于3 × 103q。由于电阻器具有较低的转换电压和电流(11V和7mA),编程容易由MOS电路控制。替换只需要15V编程脉冲,可以在晶圆探测期间完成。电阻器特性如图4所示。编程电路的A方框图如图1所示。每一个
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 256K RAM fabricated with molybdenum-polysilicon technology
128K block has two arrays of 64Kb fundamental cells and about 2Kb spare cells, and dummy sense circuit’. The spare cells are connected with four pairs of spare bit-lines and two spare word-lines. Since each pair of spare bit-lines require one additional sense amplifier, one block bas 516 amplifiers. The amplifier includes coupling capacitors, which make it possible to obtain a high refresh voltage. Amplifier circuits and operating waveforms are shown in Figure 2. The amplifier begins to detect the signal by clock @ ~ 1 , and amplification is accelerated by clock @ ~ 2 . After sensing operation the capacitors are connected with the bit-lines by clock @B. Therefore the potential of the bit-line becomes high enough for refreshing. Clock @ ~ 1 also drives the coupling capacitors. During sensing period, however, the capacitors are separated from the bitlines to prevent an increase in bit-line capacitance. As a result, this amplifier can detect a signal of ? 50mV. In the memory cell array the word line crosses over the storage capacitor electrodes, and is composed of molybdenum, which is the gate material of the cell transistor2. The bit-line is made of interconnection metal of aluminum and the storage capacitor electrode consists of polysilicon. The memory cell has been designed to obtain the signal of * 120mV in the worst case. Since both the word-line and bit-line materials are metallic, the propagation delay in the array becomes small. In other circuits Si-gate transistors are used. To improve the yield of RAMS the fault-tolerant concept is introduced. Spare cells can substitute for defective cells. This substitution is achieved by utilizing electrically programmable polysilieon resistors, which include PN junctions. Figure 3 shows the spare column decoder using these resistors. The resistance is at least 109Q initially, and it becomes less than 3 x l O 3 Q after transition. Since the resistor has low transition voltage and current (11V and 7mA), programming is controlled easily by MOS circuits. The substitution requires only 15V programming pulses and can be done during wafer probing. The resistor characteristic is shown in Figure 4. To program the A block diagram of the circuit is shown in Figure 1. Each
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