{"title":"一个400ps双极18b值","authors":"F. Sato, S. Wakamatsu, T. Kubota, K. Kimura","doi":"10.1109/ISSCC.1980.1156145","DOIUrl":null,"url":null,"abstract":"An 18b VLSI bipolar (0.4ns/2.5mW) RALU with 1300 gates and a 7ns read-modify-write cycle will be reported. Using four chips, a 72b ALU can be operated at 100MHz.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 400ps bipolar 18b RALU\",\"authors\":\"F. Sato, S. Wakamatsu, T. Kubota, K. Kimura\",\"doi\":\"10.1109/ISSCC.1980.1156145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 18b VLSI bipolar (0.4ns/2.5mW) RALU with 1300 gates and a 7ns read-modify-write cycle will be reported. Using four chips, a 72b ALU can be operated at 100MHz.\",\"PeriodicalId\":229101,\"journal\":{\"name\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"37 7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1980.1156145\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 18b VLSI bipolar (0.4ns/2.5mW) RALU with 1300 gates and a 7ns read-modify-write cycle will be reported. Using four chips, a 72b ALU can be operated at 100MHz.