采用缩放MOS技术的64K EPROM

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156041

G. Perlegos, S. Pathak, A. Renninger, W. Johnson, M. Holler, J. Skupnak, M. Reitsma, G. Kuhn

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引用次数: 7

摘要

本文将报道一种64Kb的静态MOS EPROM，它结合了两层多自对准存储单元和缩放NMOS外围技术。细胞大小为0.24μm2/b。访问时间为200ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 64K EPROM using scaled MOS technology

This paper will report on a 64Kb static MOS EPROM which combines a two-layer poly self-aligned memory cell together with scaled NMOS periphery technology. Cell size is 0.24μm2/b. Access time is 200ns.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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