2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)最新文献

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Photoluminescence parameters in strained GaAs/In/sub x/Ga/sub 1-x/As/GaAs-heterostructures 应变GaAs/ in /sub x/Ga/sub 1-x/As/GaAs异质结构的光致发光参数
N. Grigor’ev, E. Gule, A. Klimovskaya, Yu.A. Dryga, V. Litovchenko
{"title":"Photoluminescence parameters in strained GaAs/In/sub x/Ga/sub 1-x/As/GaAs-heterostructures","authors":"N. Grigor’ev, E. Gule, A. Klimovskaya, Yu.A. Dryga, V. Litovchenko","doi":"10.1109/ICMEL.2000.840574","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840574","url":null,"abstract":"The photoluminescence (PL) of In/sub x/Ga/sub 1-x/As-single quantum wells (QW) grown on GaAs substrate with x ranging between 0.16 and 0.35 was studied. The thickness (d) of QW layers was about or larger than the critical one (d/sub c/). The PL parameters were found to depend on a magnitude (d-d/sub c/)/d/sub c/ if d>d/sub c/. The heterostructures with QW-thickness d not exceeding the critical one d, meets conditions of homogeneously elastically strained heterostructures almost without defects. The energy levels in QW's and PL bands (E/sub PL/) in these heterostructures may be described theoretically, and the FWHM of the band approaches its physical limit. The heterostructures with d>d/sub c/ have a defect concentration (/spl ap/10/sup 11/ cm/sup -2/) increasing with the increase of thickness. A large long-range inhomogeneous redistribution of In atoms probably occurs in the highly strained heterostructures.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low on-resistance SOI LDMOS using a recessed source and a trench drain 一种低导通电阻SOI LDMOS,采用嵌入式源和沟槽漏极
Sung-Lyong Kim, Hoie-Yoon Yang, Yearn-Ik Choi
{"title":"A low on-resistance SOI LDMOS using a recessed source and a trench drain","authors":"Sung-Lyong Kim, Hoie-Yoon Yang, Yearn-Ik Choi","doi":"10.1109/ICMEL.2000.838772","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838772","url":null,"abstract":"An SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS using a recessed source and a trench drain is proposed to reduce the on-resistance and increase the breakdown voltage. The recessed source structure is formed by v-groove etching and the trench drain structure is formed by RIE (Reactive Ion Etching). The characteristics of the proposed LDMOS are numerically calculated by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 36.5 V VLDMOS, the on-resistance of the proposed device is decreased by 41% compared with that of the conventional device.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Impact of MOS technological parameters on the detection and modeling of the soft breakdown conduction MOS工艺参数对软击穿导通检测与建模的影响
E. Miranda, J. Suñé, R. Rodríguez, M. Nafría, X. Aymerich
{"title":"Impact of MOS technological parameters on the detection and modeling of the soft breakdown conduction","authors":"E. Miranda, J. Suñé, R. Rodríguez, M. Nafría, X. Aymerich","doi":"10.1109/ICMEL.2000.840581","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840581","url":null,"abstract":"Several models have been proposed to explain the I-V characteristic associated with the soft breakdown (SBD) failure mode in ultrathin gate oxides. However, because of the fact that the SBD experimental detection window depends not only on the technological parameters of the device under test, which set the fresh I-V characteristic of the sample, but also on the strength of the breakdown event, there is still a large disagreement about its functional form. In this paper, we show that a power law, for applied voltages less than approximately 3.5 V, and an exponential law for higher voltages are suitable fitting models.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Inverse circuit simulation method for topological delays estimation with logic simulator 基于逻辑模拟器的拓扑时延估计逆电路仿真方法
D. Maksimovic, V. Litovski
{"title":"Inverse circuit simulation method for topological delays estimation with logic simulator","authors":"D. Maksimovic, V. Litovski","doi":"10.1109/ICMEL.2000.838788","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838788","url":null,"abstract":"In this paper an original method is proposed for digital circuit topological delays estimation which is based on standard logic simulation mechanisms. The inverse circuit simulation (ICS) method is intended for interactive use in conjunction with circuit logic verification. Inverse circuit model propagates signal transitions in inverse direction: from circuit outputs toward circuit inputs. One simulator run provides the longest path delay for a chosen, rising or falling, edge at one circuit output. At the same time, the part of the circuit is detected which is the subject of redesign or delay optimization if the longest path delay does not satisfy required circuit operating frequency. Due to path reconvergence delay overestimation can occur which can be measured at each signal and propagated through the circuit together with logic states. The efficiency of the proposed method is tested on ISCAS '85 benchmark circuits.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130481249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advanced continuous-time filter design in MATLAB MATLAB中先进的连续时间滤波器设计
D. Tosic, M. Lutovac, B. Evans
{"title":"Advanced continuous-time filter design in MATLAB","authors":"D. Tosic, M. Lutovac, B. Evans","doi":"10.1109/ICMEL.2000.838798","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838798","url":null,"abstract":"We present an original software for advanced continuous-time filter design. We have written this software in MATLAB as a toolbox which we call AFDESIGN. The AFDESIGN toolbox is based on original numerical procedures rooted in Jacobi elliptic functions. The AFDESIGN toolbox finds a comprehensive set of optimal designs to represent the infinite solution space. Quite opposite, conventional approaches and commercial software packages return only one design, thereby hiding a wealth of alternative filter designs that can be more robust when implemented in hardware. The AFDESIGN toolbox is easy to use, mouse driven, and user friendly to an unexperienced filter designer or practicing engineer.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133673903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A study of varied threshold voltage MOSFET (VTMOS) performance and principle 研究了变阈值电压MOSFET (VTMOS)的性能和原理
Z. Xia, Yan Ge, Yuanfu Zhao
{"title":"A study of varied threshold voltage MOSFET (VTMOS) performance and principle","authors":"Z. Xia, Yan Ge, Yuanfu Zhao","doi":"10.1109/ICMEL.2000.840545","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840545","url":null,"abstract":"In this paper, we suggest a novel operation of a SOI MOSFET, varied threshold voltage MOSFET (VTMOS), which can work very well under ultra-low voltage(0.6 V and below) in VLSI circuits. Experiments show that the threshold voltage of the device varies with its gate voltage, which results in better performance than conventional SOI MOSFET (for example, larger drive current and lower leakage). We also provide two-dimensional (2-D) device simulation to perspective its operational principle.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132692896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of wide bandwidth, flat phase Al/sub x/O/sub y/-GaAs DBR mirrors for vertical cavity surface-emitting lasers 垂直腔面发射激光器用宽带宽、平相位Al/sub x/O/sub y/-GaAs DBR反射镜设计
A. Rakić, M. Majewski, A.B. Djurlsic, E. Li, J. Elazar
{"title":"Design of wide bandwidth, flat phase Al/sub x/O/sub y/-GaAs DBR mirrors for vertical cavity surface-emitting lasers","authors":"A. Rakić, M. Majewski, A.B. Djurlsic, E. Li, J. Elazar","doi":"10.1109/ICMEL.2000.838764","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838764","url":null,"abstract":"In this paper we develop expressions for the design of asymmetric, graded interface DBR mirrors by using the concept of characteristic matrices. This rigorous approach allowed for accurate solution of the wave equation (in both homogeneous and inhomogeneous layers) without any approximation. We investigate the two types of graded interface DBR mirrors for Vertical-Cavity Surface-Emitting Lasers: all-semiconductor DBR and oxide-semiconductor DBR. The advantages of using the wide bandwidth, flat phase oxide-semiconductor DBR mirrors over the all-semiconductor DBR mirrors have been presented.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"55 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114104920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ESD protection techniques for semiconductor devices 半导体器件的ESD保护技术
J. Vinson, J. Liou
{"title":"ESD protection techniques for semiconductor devices","authors":"J. Vinson, J. Liou","doi":"10.1109/ICMEL.2000.840579","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840579","url":null,"abstract":"Electrostatic discharges (ESD) are everywhere-in our homes, businesses and even at the manufacturers of the electronics we buy. The discharges cause failure of these electronic components. Presented here is a two pronged approach for ESD protection: reduce the likelihood of having an ESD event and improving the robustness of the devices. The first approach focuses on reducing the charge developed and controlling the redistribution of any charges that are developed. The second approach looks at ways to improve both the processes used to build electronics as well as the devices themselves.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134541187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrical characterization of ultra-shallow junctions formed by plasma immersion implantation 等离子体浸没注入形成的超浅结的电学特性
B.L. Yang, H. Wong, P. Han, M. Poon
{"title":"Electrical characterization of ultra-shallow junctions formed by plasma immersion implantation","authors":"B.L. Yang, H. Wong, P. Han, M. Poon","doi":"10.1109/ICMEL.2000.838725","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838725","url":null,"abstract":"This work reports some electrical characteristics of ultra-shallow (/spl sim/90 nm) n/sup +/p junctions fabricated using plasma immersion implantation of arsenic ions. Both forward and reverse current-voltage (IV) characteristics at operation temperatures ranging from 100 to 450 K were measured. Results show that the ideality factor varies from unity to two indicating both diffusion and GR processes are important in these devices. The ideality factor is found to fluctuate with the temperature, indicating that discrete trap centers exist in these samples. Annealing has a profound effect on the reverse diode characteristics. For fully activated sample, the IV relationship essentially follows a power law, i.e I/spl prop/V/sup m/. The power index m/spl ap/3 and almost remains unchanged at different temperatures.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133649614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Handling and assembly of functionally adapted microcomponents 处理和装配功能适应的微组件
E. Chatzitheodoridis, G. Popovic, W. Brenner, H. Detter
{"title":"Handling and assembly of functionally adapted microcomponents","authors":"E. Chatzitheodoridis, G. Popovic, W. Brenner, H. Detter","doi":"10.1109/ICMEL.2000.838757","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838757","url":null,"abstract":"HAFAM (Handling and Assembly of Functionally Adapted Microcomponents) is a network in Training and Mobility of Researchers Programme (TMR), which is the continuation of the Human Capital and Mobility (HCM) Programme of the European Commission. This paper, describes the progress of the project after 17 months of operation. The objectives are briefly mentioned, and the training effect and the implications to industry are described. Also, some of the project's scientific highlights are presented.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133807409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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