一种低导通电阻SOI LDMOS，采用嵌入式源和沟槽漏极

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI:10.1109/ICMEL.2000.838772

Sung-Lyong Kim, Hoie-Yoon Yang, Yearn-Ik Choi

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引用次数: 6

摘要

为了降低导通电阻，提高击穿电压，提出了一种采用凹槽源和沟槽漏极的横向双扩散MOS。凹源结构采用v型槽刻蚀法，沟槽漏源结构采用反应离子刻蚀法。利用二维工艺模拟器TSUPREM4和器件模拟器MEDICI对所提出的LDMOS的特性进行了数值计算。在36.5 V VLDMOS下，该器件的导通电阻比传统器件降低了41%。

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A low on-resistance SOI LDMOS using a recessed source and a trench drain

An SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS using a recessed source and a trench drain is proposed to reduce the on-resistance and increase the breakdown voltage. The recessed source structure is formed by v-groove etching and the trench drain structure is formed by RIE (Reactive Ion Etching). The characteristics of the proposed LDMOS are numerically calculated by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 36.5 V VLDMOS, the on-resistance of the proposed device is decreased by 41% compared with that of the conventional device.

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来源期刊

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)

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