A low on-resistance SOI LDMOS using a recessed source and a trench drain

Abstract

An SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS using a recessed source and a trench drain is proposed to reduce the on-resistance and increase the breakdown voltage. The recessed source structure is formed by v-groove etching and the trench drain structure is formed by RIE (Reactive Ion Etching). The characteristics of the proposed LDMOS are numerically calculated by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 36.5 V VLDMOS, the on-resistance of the proposed device is decreased by 41% compared with that of the conventional device.