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2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献

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A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier 一种新型的低功率高效率三态无滤波器D类放大器
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440257
Huiqiao He, Y. Kang, Jia Yu, Linfei Guo, T. Ge, J. Chang
{"title":"A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier","authors":"Huiqiao He, Y. Kang, Jia Yu, Linfei Guo, T. Ge, J. Chang","doi":"10.1109/ICECS.2015.7440257","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440257","url":null,"abstract":"Of the reported modulation techniques for Class D amplifiers (CDAs), CDAs based on Bang-Bang control modulation are arguably the most advantageous in terms of power-efficiency for low-power power-critical applications. To date, only single-ended and 2-state Bang-Bang control CDAs have been reported, and are hence disadvantageous because they require a bulky and costly output lowpass filter. In this paper, we propose the first-ever 3-state Bang-Bang control filterless CDA applicable to regular-power and ultra-low-power applications. Compared to other filterless 3-state CDAs, the proposed filterless 3-state Bang-Bang control CDA features the simplest hardware and the highest power-efficiency, but with somewhat compromised fidelity. Nevertheless, the fidelity thereto is sufficient for typical ultra-low-power applications such as low-to-mid performance wearable devices.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"181 S473","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel self-referenced ferroelectric-memory readout scheme 一种新的自参考铁电存储器读出方案
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440260
S. Sharroush
{"title":"A novel self-referenced ferroelectric-memory readout scheme","authors":"S. Sharroush","doi":"10.1109/ICECS.2015.7440260","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440260","url":null,"abstract":"Reading one-transistor one capacitor ferroelectric random-access memory (1T-1C FRAM) requires generating a reference voltage that is ideally halfway between the two bitline voltages generated in cases of \"1\" and \"0\" readings. However, these two generated voltages vary from cell to cell and with the process variations. So, a self-referenced scheme is needed. In this paper, a self-referenced readout scheme will be proposed that depends on properly pulsing the plateline and using a capacitive-voltage divider. The proposed scheme is verified using simulation adopting the 45 nm CMOS technology and shows a 33% reduction in the read-cycle time. Enhancing the robustness of the reading circuitry will also be investigated quantitatively.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134370363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization 专用乘法块和加法树方案的优化组合，用于优化基数-2m阵列乘法器的实现
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440321
A. Martins, M. Fonseca, E. Costa
{"title":"Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization","authors":"A. Martins, M. Fonseca, E. Costa","doi":"10.1109/ICECS.2015.7440321","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440321","url":null,"abstract":"In this paper, we seek the optimal combination of dedicated radix-2m multiplication blocks, and adder trees schemes for the realization of optimized radix-2m array multipliers. The operands of the multipliers are generated by 2's complement radix-4, radix-16, radix-256, and radix-65536 dedicated multiplication blocks. The operands are added using different adder trees schemes such as Wallace, RBA, and compressors. The number of operands defines the amount of adders blocks used in the addition tree of the array multiplier. The logic synthesis was realized using Cadence Encounter RTL Compiler tool with Nangate 45nm Open Cell library. Area, delay and power consumption results are presented for the synthesized proposed multipliers. As will be presented, the combination of radix-4 or radix-16 dedicated multiplication block and multi-operand adder tree schemes yields the best power - performance results in the radix-2m array multipliers.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131820621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Incremental layout-aware analog design methodology 增量布局感知模拟设计方法
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440354
Mohannad Elshawy, M. Dessouky
{"title":"Incremental layout-aware analog design methodology","authors":"Mohannad Elshawy, M. Dessouky","doi":"10.1109/ICECS.2015.7440354","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440354","url":null,"abstract":"With the continuous scaling of CMOS into ultra-deep sub-micron regions, various layout effects are becoming more significant. Accordingly, device characteristics and circuit performance are highly affected. This leads to difficulty in designing analog circuits as they become very sensitive to desire locations in the layout. This paper proposes a design methodology that takes into account the layout dependent effects at early stage of schematic design. Using this methodology the circuit designer will be aware of device characteristics variations such as threshold voltage and mobility. To validate the design methodology, a two stage Miller OTA using 28 nm CMOS technology is designed.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127835636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter 采用低功耗两步时间-数字转换器的宽带5ghz数字锁相环
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440315
Ahmed Hamza, S. Ibrahim, M. El-Nozahi, M. Dessouky
{"title":"A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter","authors":"Ahmed Hamza, S. Ibrahim, M. El-Nozahi, M. Dessouky","doi":"10.1109/ICECS.2015.7440315","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440315","url":null,"abstract":"This paper presents the design of a wideband, low-jitter 5 GHz digital phase-locked loop (DPLL) in 65 nm CMOS. The DPLL uses a high-resolution, low-power two-step time-to-digital converter (TDC) to achieve a wide loop bandwidth (BW) with low jitter. The DPLL is designed with a loop BW of 4 MHz using a 100 MHz reference and achieves a root mean square (RMS) jitter and a peak-to-peak (PP) jitter of 1.59 ps and 20.69 ps respectively at 5 GHz operation. The DPLL occupies an area of 0.026 mm2 and consumes 4.5 mA from a 1.2 V supply.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117311814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An evaluation of BTI degradation of 32nm standard cells 32nm标准细胞对BTI降解的评价
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440403
Rafael B. Schivittz, C. Meinhardt, P. Butzen
{"title":"An evaluation of BTI degradation of 32nm standard cells","authors":"Rafael B. Schivittz, C. Meinhardt, P. Butzen","doi":"10.1109/ICECS.2015.7440403","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440403","url":null,"abstract":"Aging effects has become a critical reliability constraints in nanometer circuits. The major aging mechanism is the BTI (Bias Temperature Instability), which increases the transistor threshold voltage, reducing system operation frequency and may generate a circuit timing violation. This work presents a tool that estimates the delay degradation due to BTI effect in CMOS logic gates. The work evaluates the delay degradation of a set of the most frequently used combinational gates from a 32nm standard library for different lifetimes. This information is used to define the more sensible gates due to aging effect, providing important information to designer.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123712790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel memristor emulator based only on an exponential amplifier and CCII+ 一种仅基于指数放大器和CCII+的新型忆阻器仿真器
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440327
Abdullah G. Alharbi, M. Fouda, M. Chowdhury
{"title":"A novel memristor emulator based only on an exponential amplifier and CCII+","authors":"Abdullah G. Alharbi, M. Fouda, M. Chowdhury","doi":"10.1109/ICECS.2015.7440327","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440327","url":null,"abstract":"This paper introduces a novel memristor emulator circuit, which consists only of an exponential amplifier and a second generation current conveyor (CCII+) to achieve the non-linearity behavior of the memristor in the I-V plane. This emulator circuit is very simple and less complex compared to the previously published circuits. Furthermore, this circuit can accurately imitate the behavior of a memristor and satisfy the fingerprints of the memristors. The paper also presents the mathematical modeling and analysis of the proposed emulator. Finally, PSPICE and analytical validations are provided to validate the proposed emulator circuit.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117093273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Evaluation of a couple of true random number generators with liberally licensed hardware, firmware, and drivers 使用自由许可的硬件、固件和驱动程序对几个真正的随机数生成器进行评估
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440282
S. Callegari
{"title":"Evaluation of a couple of true random number generators with liberally licensed hardware, firmware, and drivers","authors":"S. Callegari","doi":"10.1109/ICECS.2015.7440282","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440282","url":null,"abstract":"Sequences of high quality random bits are required in virtually all modern security and cryptography applications, pushing designers to devise hardware-based true random number generators (TRNGs). Alongside architectures made by big players of information technology and/or proposed via peer reviewed channels, many alternatives exist. The recent, powerful trend t o interconnect even humble devices creates a significant deployment space for some of them, thanks to properties such as low-cost, good suitability to augment existing hardware, and readily available hardware/firmware/driver designs with liberal licenses. Consequently, there is practical relevance in a formal evaluation of their design. In this work, the \"InfNoise\" and \"Redoubler\" open architectures are investigated, finding them to belong to the chaos-based TRNG class and to bear similarity to some academic designs from the late'90s. Despite some some margins for improvement, the designs are found to admit formal justification.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Structure optimization for efficient AlN piezoelectric energy harvesters 高效AlN压电能量采集器的结构优化
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440370
M. Shadoufa, Ahmed Emad, M. Ghoneima, M. Mahmoud, M. Dessouky
{"title":"Structure optimization for efficient AlN piezoelectric energy harvesters","authors":"M. Shadoufa, Ahmed Emad, M. Ghoneima, M. Mahmoud, M. Dessouky","doi":"10.1109/ICECS.2015.7440370","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440370","url":null,"abstract":"Lead Zirconate Titnate, or PZT, has always been favored over Aluminum Nitride, AlN, in Energy Harvesting applications due to its superior coupling coefficient, d31. However, the use of PZT in some applications, such as medical implants, is not possible due to its toxic nature as it contains Lead. In this paper, a comparison between the performances of PZT and AlN harvesters is held by utilizing the same uniform cantilever structure. The results of this comparison show that PZT has only 4 times the output power of AlN, and 33% lower resonance frequency. To further increase the output power of the AlN harvester and drive its resonance frequency down to perform PZT-like, a modification to the beam structure is proposed. The modification is to taper the cross-section of the beam linearly. The new structure has the same exact area as the uniform cantilever beam. The FEM simulation results show that the output power of the AlN harvester with the modified structure is nearly the same as the uniform PZT structure, around 1.3 μW for an input acceleration of 0.5g and the resonance frequency is even 35% lower. The gap in performance between PZT and AlN is nearly eliminated using the proposed structure without requiring extra area.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128211824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and linearity analysis of a M-2M DAC for very low supply voltage M-2M数模转换器的设计及线性度分析
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440304
Israel Sperotto, H. Klimach, S. Bampi
{"title":"Design and linearity analysis of a M-2M DAC for very low supply voltage","authors":"Israel Sperotto, H. Klimach, S. Bampi","doi":"10.1109/ICECS.2015.7440304","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440304","url":null,"abstract":"This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC) proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors are operating in the subthreshold region under such low supply, the mismatch analysis was done using an all-region continuous MOSFET model. The performance of the circuit is evaluated through simulations and the trade-offs between linearity, supply voltage and sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating under 200 mV and with sampling rate of 5.1MS/s is feasible using a commercial 130 nm process and standard transistors.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129123174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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