Incremental layout-aware analog design methodology

Abstract

With the continuous scaling of CMOS into ultra-deep sub-micron regions, various layout effects are becoming more significant. Accordingly, device characteristics and circuit performance are highly affected. This leads to difficulty in designing analog circuits as they become very sensitive to desire locations in the layout. This paper proposes a design methodology that takes into account the layout dependent effects at early stage of schematic design. Using this methodology the circuit designer will be aware of device characteristics variations such as threshold voltage and mobility. To validate the design methodology, a two stage Miller OTA using 28 nm CMOS technology is designed.