A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter

This paper presents the design of a wideband, low-jitter 5 GHz digital phase-locked loop (DPLL) in 65 nm CMOS. The DPLL uses a high-resolution, low-power two-step time-to-digital converter (TDC) to achieve a wide loop bandwidth (BW) with low jitter. The DPLL is designed with a loop BW of 4 MHz using a 100 MHz reference and achieves a root mean square (RMS) jitter and a peak-to-peak (PP) jitter of 1.59 ps and 20.69 ps respectively at 5 GHz operation. The DPLL occupies an area of 0.026 mm2 and consumes 4.5 mA from a 1.2 V supply.