Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization

Abstract

In this paper, we seek the optimal combination of dedicated radix-2m multiplication blocks, and adder trees schemes for the realization of optimized radix-2m array multipliers. The operands of the multipliers are generated by 2's complement radix-4, radix-16, radix-256, and radix-65536 dedicated multiplication blocks. The operands are added using different adder trees schemes such as Wallace, RBA, and compressors. The number of operands defines the amount of adders blocks used in the addition tree of the array multiplier. The logic synthesis was realized using Cadence Encounter RTL Compiler tool with Nangate 45nm Open Cell library. Area, delay and power consumption results are presented for the synthesized proposed multipliers. As will be presented, the combination of radix-4 or radix-16 dedicated multiplication block and multi-operand adder tree schemes yields the best power - performance results in the radix-2m array multipliers.