An evaluation of BTI degradation of 32nm standard cells

Abstract

Aging effects has become a critical reliability constraints in nanometer circuits. The major aging mechanism is the BTI (Bias Temperature Instability), which increases the transistor threshold voltage, reducing system operation frequency and may generate a circuit timing violation. This work presents a tool that estimates the delay degradation due to BTI effect in CMOS logic gates. The work evaluates the delay degradation of a set of the most frequently used combinational gates from a 32nm standard library for different lifetimes. This information is used to define the more sensible gates due to aging effect, providing important information to designer.