{"title":"Switch selection & sizing in CMOS implementation of variable output switched capacitor step-down DC-DC converter","authors":"Mahesh Zanwar, S. Sen","doi":"10.1109/ICECS.2015.7440336","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440336","url":null,"abstract":"This paper describes the CMOS implementation of an open-loop variable output voltage switched capacitor step-down DC-DC converter with large number of target voltages. The number of target voltages generated using n-flying capacitors are of the order of 2n. A scheme for selection of transistor type and size is given that optimizes silicon area and efficiency of a given design. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are derived in terms of switching frequency (Fsw), flying capacitor value and compared with the simulated results. The effect of flying capacitor on efficiency is shown with the plots of efficiency vs. output voltages and bottom plate capacitance. The 3/4 step-down converter circuit is described and analysed by varying switching frequency and load for different values of bottom plate capacitance. An efficiency of about 87% is achieved with 15% bottom plate capacitance for load current of 10mA and input voltage of 1.8V at 4MHz of switching frequency.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122930625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power 2.5-Gb/s CMOS burst-mode transimpedance amplifier with fast response time using a novel peak detection circuit","authors":"Young-Ho Kim, Eunok Kim, Wonjong Kim","doi":"10.1109/ICECS.2015.7440289","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440289","url":null,"abstract":"A 2.5 Gb/s CMOS burst-mode transimpedance amplifier (BM-TIA) with a novel peak detection circuit is designed in this paper. The proposed peak detection circuit changes quickly the gain mode of the BM-TIA and then improves the data transmission capacity of the PON system with low power consumption. In order to obtain quick response time of the BM-TIA, a RC-LPF, an amplifier followed it and a replica circuit of the amplifier are built in. This BM-TIA was fabricated in 1P6M 0.18 μm CMOS process. The designed IC exhibits a quick response of 11 nsec for a 2.5 Gb/s burst preamble input. In this condition, this chip of 4 channel consumes 195.4 mW from a 1.8 V supply. In high gain mode, the BM-TIA achieves a gain of 66 dBΩ with 2.45 GHz bandwidth and the eye jitter (rms) of 4.243 ps.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A mathematical model of an ideally threshold compensated rectifier for RF energy harvesting","authors":"Doaa M. Elgabry, M. Aboudina, E. Hegazi","doi":"10.1109/ICECS.2015.7440323","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440323","url":null,"abstract":"This paper introduces a mathematical model of an ideally threshold compensated rectifier for RF energy harvesting. The ideally compensation arrangement has been exploited to improve the rectifier's performance and overcome the limitation of rectifier's sensitivity which mainly depends on the threshold voltage of the rectifying devices (transistors). The model considers the conduction angle and the reverse current in deriving closed form analytical expressions for output dc voltage and efficiency. Using a 65-nm low leakage CMOS process with low-threshold transistors, 900-MHz multi-stages rectifiers were designed using both the proposed model and Cadence Virtuoso. The results of the model extremely match the simulation results using Cadence Virtuoso while running 100 times faster.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129800002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohammed A. El-Motaz, Ahmed M. El-Shafiey, Mohamed Farag, Omar A. Nasr, H. Fahmy
{"title":"Speeding-up fast fourier transform","authors":"Mohammed A. El-Motaz, Ahmed M. El-Shafiey, Mohamed Farag, Omar A. Nasr, H. Fahmy","doi":"10.1109/ICECS.2015.7440365","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440365","url":null,"abstract":"This work proposes a restructure of FFT algorithm to be more hardware friendly. The proposed algorithm is modeled as a combinatorial optimization problem. This paper presents two sub-optimal schemes of the proposed FFT restructure: one-stage and two-stage optimization. The proposed FFT algorithm is applied on 1024-point Radix-2 Single-Path Delay Feedback (R2SDF) architecture. The one-stage and two-stage optimization schemes achieve reduction in the multipliers area by 40.8% and 62.5%, respectively, compared with the conventional algorithm.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130256931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. A. S. Mohammed, A. Bellar, Y. Bentoutou, A. Boudjemai, R. Roubache
{"title":"A comparative study of nadir attitude pointing satellite solutions","authors":"M. A. S. Mohammed, A. Bellar, Y. Bentoutou, A. Boudjemai, R. Roubache","doi":"10.1109/ICECS.2015.7440281","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440281","url":null,"abstract":"In a variety of satellite engineering problems, analytic solutions are by far the best alternatives to spacecraft attitude dynamic equations than the numerical solutions. In this paper, a refined analytic solution in the roll and yaw axis of a nadir attitude pointing microsatellite and more specifically a passive gravity gradient stabilized microsatellite, is proposed and compared with a recent linear solution from the literature. This linear approximated solution can only be used in few limited cases; however, the proposed one is valid for the more complicated problems found in spacecraft dynamics. It is shown that such a solution is very efficient to model spacecraft attitude dynamics. Simulation results clearly indicate that the proposed analytic solution is more accurate than the existing solution in the roll and yaw axis, even when applied to the worst cases.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel scheduling algorithm for mmWave mesh networks using packet aggregation","authors":"Muhammad K. Ibrahim, M. H. Ismail, M. El-Kharashi","doi":"10.1109/ICECS.2015.7440383","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440383","url":null,"abstract":"In this paper, we address throughput improvement in a millimeter wave (mmW) mesh network via using packet aggregation and block acknowledgement that were firstly introduced in IEEE 802.11e/n. Specifically, we introduce a distributed TDM scheduling algorithm that targets achieving fairness among the nodes, increasing the air utilization via maximizing the total number of reserved slots for all nodes as well as increasing capacity by reserving the slots for each node in a contiguous fashion as much as possible to make the use of packet aggregation doable. Extensive simulations of the proposed algorithm show that it raised the network throughput by almost 70% compared to the well-known memory-guided directional MAC (MDMAC) due to reducing the transmission overhead.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117208499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Massively parallel cellular matrix model for self-organizing map applications","authors":"Hongjian Wang, Abdelkhalek Mansouri, Jean-Charles Créput","doi":"10.1109/ICECS.2015.7440384","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440384","url":null,"abstract":"We propose the concept of parallel cellular matrix which partitions the Euclidean plane defined by input data into an appropriate number of uniform cell units. Each cell is responsible of a certain part of the data and the network of the self-organizing map (SOM), and carries out massive parallel spiral searches based on the cellular matrix topology. The advantage of the proposed model is that it is decentralized and based on data decomposition. The required processing units and memory are with linearly increasing relationship to the problem size. Based on the cellular matrix model, the parallel SOM is implemented to deal with various applications including the traveling salesman problem, structured mesh generation, and superpixel adaptive segmentation map. Experimental results of our GPU implementation show that the running time increases in a linear way with a very weak increasing coefficient according to the input size. The proposed cellular matrix model is suitable to deal with large scale problems in a massively parallel way.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Ghorbel, F. Haddad, H. Barthélemy, W. Rahajandraibe, M. Loulou, H. Mnif
{"title":"Design and implementation of an inductorless digitally controlled oscillator based on CMOS inverters","authors":"I. Ghorbel, F. Haddad, H. Barthélemy, W. Rahajandraibe, M. Loulou, H. Mnif","doi":"10.1109/ICECS.2015.7440378","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440378","url":null,"abstract":"This paper presents the architecture of a digitally controlled oscillator (DCO) suitable for multi-standard radio frequency (RF) operation. The presented oscillator has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters control voltages. The oscillator can cover different frequency bands from 1.23 GHz to 2.46 GHz by varying digitally four inverters sequence. It consumes less than 4.4 mW under 1.1 V supply voltage. It occupies a chip area of (54 × 59) μm2 in 130 nm CMOS technology.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122281522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptive digital pre-distortion for future wireless transmitters","authors":"Mickaël Dardaillon, C. Jabbour, V. P. Srini","doi":"10.1109/ICECS.2015.7440316","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440316","url":null,"abstract":"Digital pre-distortion techniques are one of the most interesting approaches to break the linearity-efficiency tradeoff of Power Amplifiers. In the recent past, these techniques were exclusively employed in the base stations due to the high computation resources needed for the coefficients estimation. Nowadays, low-complexity DPD techniques are proposed to extend their usage in mobile devices such as tablets and even smartphones. In this paper, we propose a novel low-complexity DPD estimation scheme. The approach consists in using a memoryless polynomial correction to reduce the estimation run time/complexity and to perform a fast reevaluation for each LO frequency in order to mitigate the memory effects. The proposed technique was implemented and validated on PAs off-the-shelf using the AD-FMComms3-EBZ transceiver board and a Kalray MPPA platform. Adjacent Channel Power Ratio improvements of 14 dB were obtained for output powers of 22 dBm.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116049200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a 10Gsps TI-flash ADC with modified clocking scheme","authors":"Khaled A. El-Gammal, S. Ibrahim","doi":"10.1109/ICECS.2015.7440300","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440300","url":null,"abstract":"A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gsps sampling speed and a figure of merit of 115 fJ/conversion-step. It uses a modified clocking scheme that enables the usage of basic architectures for both the sample and hold and the comparator blocks, reduces the ADC power, and enhances both the resolution and accuracy without the need for digital calibration. The ADC was designed using 65nm CMOS technology and tested for input signals up to 5GHz. The reported latency for each sub-ADC output is about one and half clock cycle.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127338769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}