Design of a 10Gsps TI-flash ADC with modified clocking scheme

Abstract

A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gsps sampling speed and a figure of merit of 115 fJ/conversion-step. It uses a modified clocking scheme that enables the usage of basic architectures for both the sample and hold and the comparator blocks, reduces the ADC power, and enhances both the resolution and accuracy without the need for digital calibration. The ADC was designed using 65nm CMOS technology and tested for input signals up to 5GHz. The reported latency for each sub-ADC output is about one and half clock cycle.