Switch selection & sizing in CMOS implementation of variable output switched capacitor step-down DC-DC converter

Abstract

This paper describes the CMOS implementation of an open-loop variable output voltage switched capacitor step-down DC-DC converter with large number of target voltages. The number of target voltages generated using n-flying capacitors are of the order of 2n. A scheme for selection of transistor type and size is given that optimizes silicon area and efficiency of a given design. Expressions for equivalent series resistance (Req), conduction, switching power loss and efficiency are derived in terms of switching frequency (Fsw), flying capacitor value and compared with the simulated results. The effect of flying capacitor on efficiency is shown with the plots of efficiency vs. output voltages and bottom plate capacitance. The 3/4 step-down converter circuit is described and analysed by varying switching frequency and load for different values of bottom plate capacitance. An efficiency of about 87% is achieved with 15% bottom plate capacitance for load current of 10mA and input voltage of 1.8V at 4MHz of switching frequency.