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2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献

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Parameterized test patterns methodology for layout design rule checking verification 布局设计规则检验验证的参数化测试模式方法
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440385
M. Tantawy, R. Guindi, M. Dessouky, M. Al-Imam
{"title":"Parameterized test patterns methodology for layout design rule checking verification","authors":"M. Tantawy, R. Guindi, M. Dessouky, M. Al-Imam","doi":"10.1109/ICECS.2015.7440385","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440385","url":null,"abstract":"Design rules verification is an essential stage in the Process Design Kit (PDK) release for any fab. Since achieving high yield is the target of any fab, the design rules should ensure this. Design rules violations happening after fabrication lead to disastrous results on the mask sets as well as increased cost and delayed schedules. Here comes the importance of verifying these design rules and making sure that they represent the process in a manner that achieves a high yield and detects design rules issues early on. The verification process consumes 60% of the release cycle and the most time consuming step in the process is the Design rules checking (DRC) verification. Advanced technology nodes introduced stricter design rules as well as new design techniques, which added more complexity to the design rules development and verification. This paper presents a novel flow for automating the most time consuming part of the (DRC) rule decks verification, which is test cases creation and allows users to enhance the quality of the verification process and increase the testing coverage as well. And eventually reduces the time consumed in verification to 26% of what it was using conventional verification methods.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129603259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A hierarchical LST-based task scheduler for NoC-based MPSoCs with slack-time monitoring support 一个基于分层lst的任务调度器，用于支持空闲时间监控的基于noc的mpsoc
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440310
Marcelo Ruaro, G. Madalozzo, F. Moraes
{"title":"A hierarchical LST-based task scheduler for NoC-based MPSoCs with slack-time monitoring support","authors":"Marcelo Ruaro, G. Madalozzo, F. Moraes","doi":"10.1109/ICECS.2015.7440310","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440310","url":null,"abstract":"Emerging large-scale MPSoCs can have hundreds of PEs (Processing Elements), and scalable real-time support is necessary. Current proposals in MPSoCs scheduling have static behaviors or lack accurate validation, from a clock cycle model of the system. This paper proposes a hierarchical scheduling algorithm. At the bottom level, each PE executes a local LST-based scheduler algorithm with extended features to handle with inter-task communication and interruption overheads. At the top level, a global scheduler manages at run-time task mapping and real-time adaptation by using task migration and monitored information. The run-time adaptation is supported by a slack time monitoring that notifies the global scheduler the slack time of the PEs. The monitoring data, combined with traditional real-time metrics, provide a powerful real-time management that, as demonstrated by a clock cycle validation, can be implemented in large scale MPSoCs.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129422518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters 数据转换器误码率分析及混合信号三模冗余方法
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440338
J. Muhlestein, Hariprasath Venkatram, J. Guerber, Allen Waters, U. Moon
{"title":"Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters","authors":"J. Muhlestein, Hariprasath Venkatram, J. Guerber, Allen Waters, U. Moon","doi":"10.1109/ICECS.2015.7440338","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440338","url":null,"abstract":"This paper analyzes the effect of bit error rate on ADC performance and presents triple modular redundancy method for data converters. A comparison among different analog to digital converters (including successive approximation register, algorithmic/cyclic, and pipeline ADC architectures) are discussed. It is shown that a multi-path architecture provides the ability to measure and correct bit errors, squaring the bit error performance without additional analog area or power. We provide a comparative study of bit error rate among the different architectures and an error power calculation method that may be applied to further variations on these architectures, without time-consuming transient simulations.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124308983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Differentiation of MPSoCs message classes using multiple NoCs 使用多个noc的mpsoc消息类的区分
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440311
Douglas R. G. Silva, F. Moraes
{"title":"Differentiation of MPSoCs message classes using multiple NoCs","authors":"Douglas R. G. Silva, F. Moraes","doi":"10.1109/ICECS.2015.7440311","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440311","url":null,"abstract":"MPSoCs using a distributed memory architecture generates a large volume of messages that may be classified in application messages, as defined by the application developer, and management messages, used to ensure the correct operation of the platform. Both messages classes normally use the same communication infrastructure. Thus, the application traffic can be adversely impacted by the management traffic. Several works observe that different messages classes can be distributed into multiple NoCs, improving the performance and power consumption of the platform. However, these works mainly target shared memory systems. This work suggests the utilization of multiple NoCs in an MPSoC using distributed memory architecture, specializing each network for different message classes. An improvement of up to 40% in the application messages jitter and an average improvement of 5% in the application execution time can be achieved using this strategy.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of SiO2 thickness effect on insertion loss of CMOS 60 GHz band pass filter SiO2厚度对CMOS 60 GHz带通滤波器插入损耗影响的研究
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440292
Nessim Mahmoud, A. Barakat, A. A. El-Hameed, A. A. El-Rahman, A. Allam, R. Pokharel
{"title":"Study of SiO2 thickness effect on insertion loss of CMOS 60 GHz band pass filter","authors":"Nessim Mahmoud, A. Barakat, A. A. El-Hameed, A. A. El-Rahman, A. Allam, R. Pokharel","doi":"10.1109/ICECS.2015.7440292","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440292","url":null,"abstract":"This paper presents a study of the effect of the SiO2 substrate thickness on the insertion loss performance of half wavelength open loop resonator bandpass filter. It has been observed that the main reason for insertion loss degradation is the small thickness of SiO2. An insertion loss of -1.49dB is achieved with a SiO2 thickness of 24μm. Furthermore, an equivalent lumped circuit model of the filter is proposed to verify this observation. The S-parameters of lumped element circuit model are obtained using the ADS simulator and compared with the results obtained from the EM simulator showing good agreement.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117095511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimal design of 6T SRAM bitcells for ultra low-voltage operation 超低压运行6T SRAM位元的优化设计
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440346
Amgad A. Ghonem, Mostafa F. Farid, M. Dessouky
{"title":"Optimal design of 6T SRAM bitcells for ultra low-voltage operation","authors":"Amgad A. Ghonem, Mostafa F. Farid, M. Dessouky","doi":"10.1109/ICECS.2015.7440346","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440346","url":null,"abstract":"Embedded SRAM is involved in many low-energy applications, e.g. stand-alone wireless sensor nodes. SRAMs have the highest energy contribution in such applications. Energy consumption can be decreased by lowering the supply voltage. However, SRAM bitcells impose a lower bound on the supply voltage. In this paper, ultra low-voltage SRAM design optimization is investigated in a 65nm technology. It is shown that the bitcell design at low-voltages is fairly different than that at nominal ones. Using aggressive write/read-assist techniques, the well-known 6-transistor bitcell can operate down to 0.5V. Five different optimized design options are compared. Write-optimized bitcells are shown to be optimal for ultra low-voltage operation.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128478875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
From StarX32 to VEGA: Low-power and low-noise mixed-signal ASICs for X-ray detectors in space and medical applications 从StarX32到VEGA:用于空间和医疗应用中的x射线探测器的低功耗和低噪声混合信号asic
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440330
M. Ahangarianabhari, G. Bertuccio, S. Caccia, M. Grassi, D. Macera, P. Malcovati
{"title":"From StarX32 to VEGA: Low-power and low-noise mixed-signal ASICs for X-ray detectors in space and medical applications","authors":"M. Ahangarianabhari, G. Bertuccio, S. Caccia, M. Grassi, D. Macera, P. Malcovati","doi":"10.1109/ICECS.2015.7440330","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440330","url":null,"abstract":"Mixed-signal ASICs are essential for reading out large X-ray spectroscopic detectors in different fields, including space and medical applications. The pixels size reduction and the detector area increase in the newest instruments make the design of the read-out ASIC extremely challenging. Indeed, a large number of channels including low-noise front-end circuits, ADCs, and back-end digital circuits have to coexist on the same chip. In this paper we discuss the challenges of designing ASICs for large area X-ray detectors, using two actual examples: StarX32 and VEGA.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122894008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ultra-low power CMOS voltage reference for high temperature applications up to 300°C 超低功耗CMOS电压基准，适用于高达300°C的高温应用
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440253
Ahmad Hassan, B. Gosselin, M. Sawan
{"title":"Ultra-low power CMOS voltage reference for high temperature applications up to 300°C","authors":"Ahmad Hassan, B. Gosselin, M. Sawan","doi":"10.1109/ICECS.2015.7440253","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440253","url":null,"abstract":"A voltage reference circuit dedicated for high temperature applications is presented. A high-temperature operation range up to 300°C and an ultra-low-power consumption of 6 μA @ 25°C and 18 μA @ 300°C are achieved by the presented new circuit which is implemented in 0.18 μm CMOS standard technology occupying layout area of 0.00063 mm2. The proposed voltage reference is based on the weighted difference of the gate-sources of NMOS and PMOS transistors operating in weak-inversion region. A reference voltage of 1.375 V is obtained with a temperature coefficient of 25 ppm/°C in a wide temperature range from 0°C to 280°C and 89 ppm/°C @ 300°C. The measured noise densities with a 100nF filtering capacitor are 80 nV/sqrt Hz and 1 nV/sqrt Hz at 100 Hz and 100 kHz respectively, and with a power-supply rejection ration (PSRR) better than -33 dB at 10 MHz.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125269726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a wideband CMOS LNA for low frequency band SKA application 用于低频SKA应用的宽带CMOS LNA设计
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440380
Eman O. Farhat, K. Adami, O. Casha, I. Grech, J. B. D. Vaate
{"title":"Design of a wideband CMOS LNA for low frequency band SKA application","authors":"Eman O. Farhat, K. Adami, O. Casha, I. Grech, J. B. D. Vaate","doi":"10.1109/ICECS.2015.7440380","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440380","url":null,"abstract":"This paper presents the design of a wideband (50-350 MHz) low noise amplifier (LNA), employing a bandwidth constrained noise figure optimization technique targeted for a low frequency band Square Kilometer Array radio telescope. In this application, noise figure and power consumption optimization is crucial. In fact, the LNA optimization and analysis considers the effect of the induced gate noise in the MOS devices. The LNA is designed in a standard 0.18 μm CMOS process and provides a forward gain higher than 30 dB across the whole bandwidth, with a noise figure of less than 0.65 dB while consuming 72 mW from a 1.5 V supply.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115831594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wide band LC VCO with automatic amplitude controller for IEEE 802.22 cognitive radio receiver 带自动幅度控制器的宽带LC压控振荡器，用于IEEE 802.22认知无线电接收机
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440376
M. Kanoun, H. Daoud, H. Mnif, M. Loulou
{"title":"Wide band LC VCO with automatic amplitude controller for IEEE 802.22 cognitive radio receiver","authors":"M. Kanoun, H. Daoud, H. Mnif, M. Loulou","doi":"10.1109/ICECS.2015.7440376","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440376","url":null,"abstract":"This paper deals with the design of an LC Voltage Controlled Oscillator (LC VCO) with and without an Automatic Amplitude Controller (AAC). In order to achieve a wide band tuning range specified in IEEE 802.22 the VCO core incorporates a Switched Capacitor Array (SCA). An amplitude controlling technique is used to stabilize the oscillation amplitude over the frequency band. The LC VCO with an AAC circuit achieves 63% of tuning range and displays phase noise levels from -126.2 dBc/Hz to -122.67 dBc/Hz at 1 MHz frequency offset within the entire tuning range. The average power consumption of the oscillator with an AAC is 21 mW.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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