超低功耗CMOS电压基准,适用于高达300°C的高温应用

Ahmad Hassan, B. Gosselin, M. Sawan
{"title":"超低功耗CMOS电压基准,适用于高达300°C的高温应用","authors":"Ahmad Hassan, B. Gosselin, M. Sawan","doi":"10.1109/ICECS.2015.7440253","DOIUrl":null,"url":null,"abstract":"A voltage reference circuit dedicated for high temperature applications is presented. A high-temperature operation range up to 300°C and an ultra-low-power consumption of 6 μA @ 25°C and 18 μA @ 300°C are achieved by the presented new circuit which is implemented in 0.18 μm CMOS standard technology occupying layout area of 0.00063 mm2. The proposed voltage reference is based on the weighted difference of the gate-sources of NMOS and PMOS transistors operating in weak-inversion region. A reference voltage of 1.375 V is obtained with a temperature coefficient of 25 ppm/°C in a wide temperature range from 0°C to 280°C and 89 ppm/°C @ 300°C. The measured noise densities with a 100nF filtering capacitor are 80 nV/sqrt Hz and 1 nV/sqrt Hz at 100 Hz and 100 kHz respectively, and with a power-supply rejection ration (PSRR) better than -33 dB at 10 MHz.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ultra-low power CMOS voltage reference for high temperature applications up to 300°C\",\"authors\":\"Ahmad Hassan, B. Gosselin, M. Sawan\",\"doi\":\"10.1109/ICECS.2015.7440253\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A voltage reference circuit dedicated for high temperature applications is presented. A high-temperature operation range up to 300°C and an ultra-low-power consumption of 6 μA @ 25°C and 18 μA @ 300°C are achieved by the presented new circuit which is implemented in 0.18 μm CMOS standard technology occupying layout area of 0.00063 mm2. The proposed voltage reference is based on the weighted difference of the gate-sources of NMOS and PMOS transistors operating in weak-inversion region. A reference voltage of 1.375 V is obtained with a temperature coefficient of 25 ppm/°C in a wide temperature range from 0°C to 280°C and 89 ppm/°C @ 300°C. The measured noise densities with a 100nF filtering capacitor are 80 nV/sqrt Hz and 1 nV/sqrt Hz at 100 Hz and 100 kHz respectively, and with a power-supply rejection ration (PSRR) better than -33 dB at 10 MHz.\",\"PeriodicalId\":215448,\"journal\":{\"name\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2015.7440253\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2015.7440253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种适用于高温应用的基准电压电路。该电路采用0.18 μm CMOS标准工艺,设计面积为0.00063 mm2,可实现高达300°C的高温工作范围和6 μA @ 25°C和18 μA @ 300°C的超低功耗。该基准电压基于工作在弱反转区的NMOS和PMOS晶体管栅极源的加权差。参考电压为1.375 V,温度系数为25 ppm/°C,温度范围为0°C至280°C, 89 ppm/°C @ 300°C。100nF滤波电容在100hz和100khz时的实测噪声密度分别为80 nV/sqrt Hz和1 nV/sqrt Hz,在10mhz时的电源抑制比(PSRR)优于-33 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Ultra-low power CMOS voltage reference for high temperature applications up to 300°C
A voltage reference circuit dedicated for high temperature applications is presented. A high-temperature operation range up to 300°C and an ultra-low-power consumption of 6 μA @ 25°C and 18 μA @ 300°C are achieved by the presented new circuit which is implemented in 0.18 μm CMOS standard technology occupying layout area of 0.00063 mm2. The proposed voltage reference is based on the weighted difference of the gate-sources of NMOS and PMOS transistors operating in weak-inversion region. A reference voltage of 1.375 V is obtained with a temperature coefficient of 25 ppm/°C in a wide temperature range from 0°C to 280°C and 89 ppm/°C @ 300°C. The measured noise densities with a 100nF filtering capacitor are 80 nV/sqrt Hz and 1 nV/sqrt Hz at 100 Hz and 100 kHz respectively, and with a power-supply rejection ration (PSRR) better than -33 dB at 10 MHz.
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