2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献_第8页

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs 提高像素探测器读出集成电路辐射硬度的双冗余设计方法

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440332

L. Frontini, V. Liberali, S. Shojaii, A. Stabile

引用次数: 0

An alternative to CMOS stacks based on a floating-gate transistor 一种基于浮栅晶体管的CMOS堆叠替代方案

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440261

S. Sharroush

引用次数: 1

Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGA 软件无线电在FPGA上实现的动态部分重构技术的性能评价

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440279

Amr Hassan, Ramy Ahmed, H. Mostafa, H. Fahmy, A. Hussien

引用次数: 17

Accelerating electromagnetic simulations: A hardware emulation approach 加速电磁仿真:一种硬件仿真方法

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440386

M. Ziad, Y. Alkabani, M. El-Kharashi, K. Salah, Mohamed Abdelsalam

引用次数: 1

Enhancement of mobile development of brain-computer platforms 加强脑机平台的移动开发

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440355

Amr S. Elsawy, S. Eldawlatly, M. Taher, G. Aly

引用次数: 2

Impact of technology scaling on the minimum energy point for FinFET based flip-flops 技术缩放对基于FinFET的触发器最小能量点的影响

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440348

Osama Abdelkader, H. Mostafa, H. A. Elhamid, A. Soliman

{"title":"Impact of technology scaling on the minimum energy point for FinFET based flip-flops","authors":"Osama Abdelkader, H. Mostafa, H. A. Elhamid, A. Soliman","doi":"10.1109/ICECS.2015.7440348","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440348","url":null,"abstract":"Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116068727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On the use of dynamic partial reconfiguration for multi-band/multi-standard software defined radio 动态部分重构在多波段/多标准软件无线电中的应用

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440359

A. Sadek, H. Mostafa, A. Nassar

引用次数: 2

Hardware/software co-design of a dynamically configurable SHA-3 System-on-Chip (SoC) 动态配置SHA-3片上系统(SoC)的软硬件协同设计

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440392

K. E. Ahmed, Mohammed M. Farag

{"title":"Hardware/software co-design of a dynamically configurable SHA-3 System-on-Chip (SoC)","authors":"K. E. Ahmed, Mohammed M. Farag","doi":"10.1109/ICECS.2015.7440392","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440392","url":null,"abstract":"In this paper, we present a novel design of a dynamically configurable hardware accelerator for the new NIST SHA-3 standard, namely the Keccak hashing function. The SHA-3 accelerator is composed of a static datapath built based on two different folded architectures of the Keccak function and controlled by a programmable Finite State Machine (FSM) that can be dynamically configured at run-time to hash a message of arbitrary size and digest length. The proposed hardware architectures enable implementing all functions and modes of operation supported by the Keccak SHA-3 hashing standard. Two prototypes of the accelerator are developed and validated on a Xilinx Virtex-6 FPGA kit as a stand-alone system and on a ZedBoard kit featuring a ZynQ-7000 SoC FPGA, where the SHA-3 accelerator is implemented in the programmable logic and interfaced to an ARM Cortex-A9 processor. Hardware implementation is followed by a hardware/software co-design of a SHA-3 SoC running the keyed-Hash Message Authentication Code (HMAC) and Pseudo-Random Number Generator (PRNG) security applications. The ARM processor runs the application software and offloads SHA-3 computations to the hardware accelerator. The implementation results illustrate the performance enhancement of the SHA-3 SoC over pure software implementations in addition to the unprecedented flexibility offered by the proposed accelerators.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124956928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder 基于8×8 Hadamard变换的HEVC编码器SATD硬件架构

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440382

Bianca Silveira, C. Diniz, M. Fonseca, E. Costa

引用次数: 15

Phase based detection of JPEG counter forensics 基于相位检测的JPEG反取证

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440243

G. Fahmy, A. Alqallaf, R. Würtz

引用次数: 3