2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献_第7页

Towards real-time neuronal connectivity assessment: A scalable pipelined parallel generalized partial directed coherence engine 迈向实时神经元连通性评估:一个可扩展的流水线并行广义部分定向相干引擎

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440237

G. Georgis, Georgios Menoutis, D. Reisis, K. Tsakalis, A. B. Shafique

引用次数: 1

Gaussian random number generator design based on double non-uniform segmentation 基于双非均匀分割的高斯随机数发生器设计

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440395

Souhail Haggui, F. Rouissi, Y. Mlayeh, F. Tlili

引用次数: 2

A configurable transmitter architecture & organization for XG-PON OLT/ONU/ONT network elements 用于XG-PON OLT/ONU/ONT网元的可配置发射机架构和组织

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440406

Georgios Menoutis, Andreas Foteas, N. Liakopoulos, G. Georgis, D. Reisis, G. Synnefakis

{"title":"A configurable transmitter architecture & organization for XG-PON OLT/ONU/ONT network elements","authors":"Georgios Menoutis, Andreas Foteas, N. Liakopoulos, G. Georgis, D. Reisis, G. Synnefakis","doi":"10.1109/ICECS.2015.7440406","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440406","url":null,"abstract":"The XG-PON standard for Passive Optical Networks (PONs) imposed high performance requirements for network equipment. Especially, the 10G transmitter designs of the office equipment (OLT), the terminals and the network units (ONTs and ONUs) become quite demanding because of the real-time requirements for preparing a frame. The current paper introduces a three layer architecture, scalable with respect to the bandwidth and suitable to realize the transmitter of the XG-PON OLT/ONT/ONU elements. The architecture's upper layer decides what data packets will be transmitted. The second layer's microsequencer commands the lowest layer's modules, which produce and locally store all the data packets to be transmitted. The three layer approach allows the architecture to be configured and organized as either an OLT transmitter or an ONU/ONT transmitter; and to be scalable and perform the functions of the OLT at 10 Gbps and those of an ONU/ONT at 2.5 Gbps. The implementation of a XG-PON ONU transmitter on Xilinx Virtex7 verifies the approach.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123569276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A CMOS based operational floating current conveyor and its applications 一种基于CMOS的可操作浮流输送机及其应用

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440357

Nermine M. Edward, Y. Ghallab, H. Mostafa, Y. Ismail

引用次数: 1

Binary floating point verification using random test vector generation based on SV constraints 基于SV约束的随机测试向量生成二进制浮点验证

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440341

Khaled Nouh, H. Fahmy

引用次数: 2

1.55-μm Dilute Nitride SOAs with low temperature sensitivity for coolerless on-chip operation 1.55 μm稀氮化soa具有低温敏感性，用于无冷却器片上操作

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440407

G. Giannoulis, N. Iliadis, D. Apostolopoulos, P. Bakopoulos, H. Avramopoulos, V. Korpijarvi, Jaakko Makela, J. Viheriala, M. Guina

引用次数: 1

Low pass filter design based on fractional power chebyshev polynomial 基于分数阶功率切比雪夫多项式的低通滤波器设计

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440236

A. M. Abdelaty, A. Soltan, Waleed A. Ahmed, A. Radwan

引用次数: 7

Parallel overloaded CDMA interconnect (OCI) bus architecture for on-chip communications 片上通信的并行过载CDMA互连(OCI)总线结构

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440393

K. E. Ahmed, Mohammed M. Farag

{"title":"Parallel overloaded CDMA interconnect (OCI) bus architecture for on-chip communications","authors":"K. E. Ahmed, Mohammed M. Farag","doi":"10.1109/ICECS.2015.7440393","DOIUrl":"https://doi.org/10.1109/ICECS.2015.7440393","url":null,"abstract":"On-chip interconnects are the performance bottleneck in modern System-on-Chips (SoCs). Bus topologies and Networks-on-Chip (NoCs) are the main approaches used to implement on-chip communication. The interconnect fabric enables resource sharing by Time and/or Space Division Multiple Access (T/SDMA) techniques. Code Division Multiple Access (CDMA) has been proposed to enable resource sharing in on-chip interconnects where each data bit is spread by a unique orthogonal spreading code of length N. Unlike T/SDMA, in wireless CDMA, the communication channel capacity can be increased by overcoming the Multiple Access Interference (MAI) problem. In response, we present two overload CDMA interconnect (OCI) bus architectures, namely TDMA-OCI (T-OCI) and Parallel-OCI (P-OCI) to increase the classical CDMA interconnect capacity. We implement and validate the T-OCI and P-OCI bus topologies on the Xilinx Artix-7 AC701 kit. We compare the basic SDMA, TDMA, and CDMA buses and evaluate the OCI buses in terms of the resource utilization and bus bandwidth. The results show that the T-OCI achieve 100% higher bus capacity, 31% less resource utilization compared to the conventional CDMA bus topology. The P-OCI bus provides N times higher bus bandwidth compared to the T-OCI bus at the expense of increased resource utilization.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130507666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Offset reduction on memristor emulator circuits 忆阻器仿真电路的偏移减小

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440307

C. Sánchez-López, M. A. Carrasco-Aguilar, F. E. Morales-Lopez

引用次数: 11

Automated analog circuit design and chip layout tool 自动化模拟电路设计和芯片布局工具

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI: 10.1109/ICECS.2015.7440353

F. Farag, M. Ibrahim, M. Shehata

引用次数: 0