Binary floating point verification using random test vector generation based on SV constraints

Abstract

Verification of Binary Floating Point (FP) Arithmetic requires robust techniques to prove compliance with Floating point IEEE Standard (IEEE Std 754-2008). This paper provides a new verification methodology that uses a constraint based random technique to generate test vectors for validating FP arithmetic instructions. The new proposal is generic and can be used to verify any software or hardware binary FP design. The constraints used in verification are written in System Verilog (SV) language and can be solved with any SV constraint solver tool. The paper provides a case study to prove the feasibility and usefulness of the proposed approach in finding bugs for Addition-Subtraction and Multiplication operations.