Offset reduction on memristor emulator circuits

Abstract

A technique for reducing the offset at the frequency-dependent pinched hysteresis loop of memristor emulator circuits is introduced. The technique involves at integrating two DC voltage sources in the emulator circuits, keeping not only the circuit size reasonable, but also the original behavior equation of the memristor emulator circuits is not drastically modified. Using this technique, we will show how the offset is reduced due to the nonlinearities of the integrator circuit and of the multiplying core, principally. The technique is applicable to floating and grounded memristor emulator circuits, whose design is based on analog multipliers.