{"title":"一种基于浮栅晶体管的CMOS堆叠替代方案","authors":"S. Sharroush","doi":"10.1109/ICECS.2015.7440261","DOIUrl":null,"url":null,"abstract":"Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An alternative to CMOS stacks based on a floating-gate transistor\",\"authors\":\"S. Sharroush\",\"doi\":\"10.1109/ICECS.2015.7440261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.\",\"PeriodicalId\":215448,\"journal\":{\"name\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2015.7440261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2015.7440261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An alternative to CMOS stacks based on a floating-gate transistor
Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.