一种基于浮栅晶体管的CMOS堆叠替代方案

S. Sharroush
{"title":"一种基于浮栅晶体管的CMOS堆叠替代方案","authors":"S. Sharroush","doi":"10.1109/ICECS.2015.7440261","DOIUrl":null,"url":null,"abstract":"Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.","PeriodicalId":215448,"journal":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An alternative to CMOS stacks based on a floating-gate transistor\",\"authors\":\"S. Sharroush\",\"doi\":\"10.1109/ICECS.2015.7440261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.\",\"PeriodicalId\":215448,\"journal\":{\"name\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2015.7440261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2015.7440261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

由于n通道(NMOS)或p通道(PMOS)堆叠,具有宽风扇的互补金属氧化物半导体(CMOS)电路的响应速度相对较慢。在本文中,将提出一种新的电路,作为CMOS堆栈的替代方案。所提出的方案是基于使用具有可变电阻作为其两个电阻之一的分压器。这个可变电阻只不过是一个浮栅MOS晶体管(FGMOS),其控制门连接到输入端。该方案将采用45纳米CMOS技术,在1 V的电源电压下进行仿真。该方案在输入数超过4个时平均延时节省,在输入数超过7个时能量延时积节省。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An alternative to CMOS stacks based on a floating-gate transistor
Complementary metal-oxide semiconductor (CMOS) circuits with wide fan in certainly suffers from the relatively slow response due to the N-channel (NMOS) or P-channel (PMOS) stack. In this paper, a novel circuit that acts as an alternative to CMOS stacks will be presented. The proposed scheme is based on using a voltage divider that has a variable resistor as one of its two resistors. This variable resistor is nothing but a floating-gate MOS transistor (FGMOS) whose control gates are connected to the inputs. The proposed scheme will be simulated using the 45 nm CMOS technology with a power-supply voltage of 1 V. The proposed scheme shows an average time-delay saving when the number of the inputs exceeds 4 and an energy-delay product saving when the number of the inputs exceeds 7.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信