Optimal design of 6T SRAM bitcells for ultra low-voltage operation

Abstract

Embedded SRAM is involved in many low-energy applications, e.g. stand-alone wireless sensor nodes. SRAMs have the highest energy contribution in such applications. Energy consumption can be decreased by lowering the supply voltage. However, SRAM bitcells impose a lower bound on the supply voltage. In this paper, ultra low-voltage SRAM design optimization is investigated in a 65nm technology. It is shown that the bitcell design at low-voltages is fairly different than that at nominal ones. Using aggressive write/read-assist techniques, the well-known 6-transistor bitcell can operate down to 0.5V. Five different optimized design options are compared. Write-optimized bitcells are shown to be optimal for ultra low-voltage operation.