加速快速傅里叶变换

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2015-12-01 DOI:10.1109/ICECS.2015.7440365

Mohammed A. El-Motaz, Ahmed M. El-Shafiey, Mohamed Farag, Omar A. Nasr, H. Fahmy

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引用次数: 1

摘要

这项工作提出了一个重构FFT算法，使其更加硬件友好。该算法被建模为一个组合优化问题。本文给出了所提出的FFT重构的两种次优方案:一阶段优化和两阶段优化。提出的FFT算法应用于1024点基数-2单路径延迟反馈(R2SDF)架构。一阶段和两阶段优化方案与常规算法相比，乘法器面积分别减少40.8%和62.5%。

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Speeding-up fast fourier transform

This work proposes a restructure of FFT algorithm to be more hardware friendly. The proposed algorithm is modeled as a combinatorial optimization problem. This paper presents two sub-optimal schemes of the proposed FFT restructure: one-stage and two-stage optimization. The proposed FFT algorithm is applied on 1024-point Radix-2 Single-Path Delay Feedback (R2SDF) architecture. The one-stage and two-stage optimization schemes achieve reduction in the multipliers area by 40.8% and 62.5%, respectively, compared with the conventional algorithm.

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来源期刊

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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