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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)最新文献

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Architecture of cluster-based FPGAs with memory 基于集群的内存fpga结构
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852633
Jason P. Clifford, S. Wilton
{"title":"Architecture of cluster-based FPGAs with memory","authors":"Jason P. Clifford, S. Wilton","doi":"10.1109/CICC.2000.852633","DOIUrl":"https://doi.org/10.1109/CICC.2000.852633","url":null,"abstract":"Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"17 1","pages":"131-134"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74731221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new approach to fully integrated CMOS LC-oscillators with a very large tuning range 一种完全集成具有非常大调谐范围的CMOS lc振荡器的新方法
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852733
F. Herzel, Heide Erzgraeber, N. Ilkov
{"title":"A new approach to fully integrated CMOS LC-oscillators with a very large tuning range","authors":"F. Herzel, Heide Erzgraeber, N. Ilkov","doi":"10.1109/CICC.2000.852733","DOIUrl":"https://doi.org/10.1109/CICC.2000.852733","url":null,"abstract":"We describe a new approach to fully integrated CMOS LC-oscillators with very large tuning range. An experimental oscillator is tunable from 1.34 GHz to 2.14 GHz. The standard deviation of the oscillation period due to thermal device noise is below 250 ppm. Potential applications include wideband RF systems and clock generation in microprocessors.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"3 1","pages":"573-576"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79087608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator 一种用于5 mcps DS-CDMA解调器的2 v 3.7 mw延迟锁相环，采用循环积分器相关器
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852613
Y. Fujimoto, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz
{"title":"A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator","authors":"Y. Fujimoto, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz","doi":"10.1109/CICC.2000.852613","DOIUrl":"https://doi.org/10.1109/CICC.2000.852613","url":null,"abstract":"A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"72 1","pages":"35-38"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89837369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-power system-on-chip for the documentation of road accidents 用于记录交通事故的低功耗芯片系统
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852653
L. Bolcioni, R. Guerrieri
{"title":"A low-power system-on-chip for the documentation of road accidents","authors":"L. Bolcioni, R. Guerrieri","doi":"10.1109/CICC.2000.852653","DOIUrl":"https://doi.org/10.1109/CICC.2000.852653","url":null,"abstract":"The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"7 1","pages":"223-226"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91030747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video 媒体处理器核心架构为实时、双向MPEG4/H。26X编解码器，30帧/秒的cif视频
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852711
T. Kamemaru, H. Ohira, H. Suzuki, K. Asano, M. Yoshimoto, Tokumichi Murakami
{"title":"Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video","authors":"T. Kamemaru, H. Ohira, H. Suzuki, K. Asano, M. Yoshimoto, Tokumichi Murakami","doi":"10.1109/CICC.2000.852711","DOIUrl":"https://doi.org/10.1109/CICC.2000.852711","url":null,"abstract":"We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"69 1","pages":"473-476"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85062300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home 9-M tr接入网片上系统，用于家庭兆比特互联网接入
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852655
S. Kozu, T. Aramaki, C. Ikeda, Yasuaki Kuroda, S. Kawanago, Mitsuji Okada, H. Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii
{"title":"A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home","authors":"S. Kozu, T. Aramaki, C. Ikeda, Yasuaki Kuroda, S. Kawanago, Mitsuji Okada, H. Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii","doi":"10.1109/CICC.2000.852655","DOIUrl":"https://doi.org/10.1109/CICC.2000.852655","url":null,"abstract":"In this paper, an access network controller for ADSL (asymmetric digital subscriber line) is described. It consists of a VR4120 MPU core, a system controller, an Ethernet controller, an ATM (asynchronous transfer mode) cell processor, a USB (universal serial bus interface) controller, and other blocks. This controller, along with ADSL PHY devices, can provide a total solution for ADSL modem and ADSL router.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84897419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced compact model for short-channel MOS transistors 先进的短沟道MOS晶体管紧凑模型
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852650
O. C. Gouveia-Filho, A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro
{"title":"Advanced compact model for short-channel MOS transistors","authors":"O. C. Gouveia-Filho, A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/CICC.2000.852650","DOIUrl":"https://doi.org/10.1109/CICC.2000.852650","url":null,"abstract":"This paper introduces the advanced compact MOSFET (ACM) model, a physically based model of the MOS transistor, derived from the long-channel transistor model presented by Cunha et al. (1998). The ACM model is composed of very simple expressions, is valid for any inversion level, conserves charge and preserves the source-drain symmetry of the transistor. Short-channel effects are included using a compact and physical approach. The performance of the ACM model in benchmark tests demonstrates its suitability for circuit simulation.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"19 1","pages":"209-212"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84215550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator 基于2v, 3.2 ps抖动，1ghz时钟合成器和温度补偿可调振荡器的CMOS DLL
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852688
David J. Foley, M. Flynn
{"title":"CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator","authors":"David J. Foley, M. Flynn","doi":"10.1109/CICC.2000.852688","DOIUrl":"https://doi.org/10.1109/CICC.2000.852688","url":null,"abstract":"This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"15 1","pages":"371-374"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73281692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 141
Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems 锁相和锁延迟系统的非线性行为建模与仿真
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852705
Lin Wu, Huawen Jin, W. Black
{"title":"Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems","authors":"Lin Wu, Huawen Jin, W. Black","doi":"10.1109/CICC.2000.852705","DOIUrl":"https://doi.org/10.1109/CICC.2000.852705","url":null,"abstract":"This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"120 1","pages":"447-450"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74653889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI 动态可重构逻辑引擎(DRLE) LSI上实际应用的时空映射
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852638
K. Furuta, T. Fujii, M. Motomura, K. Wakabayashi, M. Yamashina
{"title":"Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI","authors":"K. Furuta, T. Fujii, M. Motomura, K. Wakabayashi, M. Yamashina","doi":"10.1109/CICC.2000.852638","DOIUrl":"https://doi.org/10.1109/CICC.2000.852638","url":null,"abstract":"We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power /spl mu/P in both performance and energy consumption. We believe DRLE's scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73667125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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