A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator

Abstract

A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.