Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

K. Furuta, T. Fujii, M. Motomura, K. Wakabayashi, M. Yamashina
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引用次数: 21

Abstract

We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power /spl mu/P in both performance and energy consumption. We believe DRLE's scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs.
动态可重构逻辑引擎(DRLE) LSI上实际应用的时空映射
我们使用DES和Reed-Solomon应用程序来评估动态可重构逻辑引擎(DRLE) LSI,并将这些应用程序在空间上映射和时间上划分为DRLE LSI的多个上下文。评估结果表明,与传统的低功耗/spl mu/P相比,DRLE在性能和能耗方面都提高了一个数量级以上。我们相信,通过在多种环境中动态重新配置,DRLE对各种大小应用程序的可扩展性将对系统lsi中的片上可编程IP核具有不可估量的价值。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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