锁相和锁延迟系统的非线性行为建模与仿真

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852705

Lin Wu, Huawen Jin, W. Black

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引用次数: 10

摘要

本文提出了一种新的VCO和电压控制延迟线(VCDL)电路建模方法，该方法允许通过简化的数值计算来包含器件噪声和电源耦合效应。锁相环和DLL行为模拟允许在锁定和解锁条件下准确预测系统性能，大大减少了晶体管级模拟器的CPU时间。仿真结果与理论预测和实测结果进行了比较，验证了该方案的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems

This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.

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来源期刊

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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