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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)最新文献

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Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies 使用标准ASIC库元素、工具和设计方法设计高速串行端口
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852654
Paul Freud
{"title":"Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies","authors":"Paul Freud","doi":"10.1109/CICC.2000.852654","DOIUrl":"https://doi.org/10.1109/CICC.2000.852654","url":null,"abstract":"This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"34 1","pages":"227-230"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89983062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An integrated capacitively coupled transformer and its application for RF IC's 一种集成电容耦合变压器及其在射频集成电路中的应用
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852682
L. Wong, C. Snyder, T. Manku, S. Kovacic
{"title":"An integrated capacitively coupled transformer and its application for RF IC's","authors":"L. Wong, C. Snyder, T. Manku, S. Kovacic","doi":"10.1109/CICC.2000.852682","DOIUrl":"https://doi.org/10.1109/CICC.2000.852682","url":null,"abstract":"This paper describes a low voltage topology that uses a passive element that is described as a \"capacitively coupled transformer\" (CCT). This structure can be easily implemented using an IC technology that supports both on chip MIM capacitors and high Q-inductors. The structure is used to design a low noise amplifier at 1.9 GHz. The LNA consumes 4 mA of current has a input IP3 of -4.5 dBm, a noise figure of 2.3 dB for a source resistance of 50 /spl Omega/, a minimum noise figure of 1.9 dB, and a gain of 10.1 dB. The topology maintains a high linearity without sacrificing noise figure and gain for a supply voltage of 1 V.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"1 1","pages":"349-352"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75826580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Ultra low-power CMOS IC using partially-depleted SOI technology 超低功耗CMOS集成电路采用部分耗尽SOI技术
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852617
A. Ebina, T. Kadowaki, Y. Sato, M. Yamaguchi
{"title":"Ultra low-power CMOS IC using partially-depleted SOI technology","authors":"A. Ebina, T. Kadowaki, Y. Sato, M. Yamaguchi","doi":"10.1109/CICC.2000.852617","DOIUrl":"https://doi.org/10.1109/CICC.2000.852617","url":null,"abstract":"We have developed an ultra low power IC for wrist-watch application. The realized operation current and voltage were 30 nA and 0.42 V respectively. This extremely low power operation was achieved by taking full advantage of body-floated devices with the partially-depleted SOI CMOS technology.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"19 1","pages":"57-60"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75690173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
MOS transistor modeling for RF integrated circuit design 用于射频集成电路设计的MOS晶体管建模
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852646
C. Enz
{"title":"MOS transistor modeling for RF integrated circuit design","authors":"C. Enz","doi":"10.1109/CICC.2000.852646","DOIUrl":"https://doi.org/10.1109/CICC.2000.852646","url":null,"abstract":"The design of radio-frequency (RF) integrated circuits in deep-submicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and even beyond. Unfortunately, the currently available compact models give inaccurate results if they are not modified adequately. This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical and scalable equivalent circuit that can easily be implemented as a Spice subcircuit is described. The small-signal, noise and large-signal operations are discussed and measurements made on a 0.25 /spl mu/m CMOS process are presented that validate the RF MOS model up to 10 GHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"6 1","pages":"189-196"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84263900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Analysis of jitter due to power-supply noise in phase-locked loops 锁相环中电源噪声引起的抖动分析
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852704
P. Heydari, M. Pedram
{"title":"Analysis of jitter due to power-supply noise in phase-locked loops","authors":"P. Heydari, M. Pedram","doi":"10.1109/CICC.2000.852704","DOIUrl":"https://doi.org/10.1109/CICC.2000.852704","url":null,"abstract":"Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 /spl mu/m CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"34 1","pages":"443-446"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79750700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A broadband 10 GHz track-and-hold in Si/SiGe HBT technology 一种宽带10ghz的Si/SiGe HBT跟踪保持技术
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852658
J. Jensen, L. Larson
{"title":"A broadband 10 GHz track-and-hold in Si/SiGe HBT technology","authors":"J. Jensen, L. Larson","doi":"10.1109/CICC.2000.852658","DOIUrl":"https://doi.org/10.1109/CICC.2000.852658","url":null,"abstract":"This paper presents a track-and-hold amplifier for sub-sampling communications applications based on a diode bridge design with high-speed Schottky diodes. Implemented in a 45 GHz BiCMOS Si/SiGe process, this IC consumes approximately 550 mW and can accommodate input voltages up to 600 mV. It has an IIP3 of 25.7 dBm with an input bandwidth in excess of 10 GHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"68 1","pages":"245-248"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81404524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
WiCkeD: analog circuit synthesis incorporating mismatch WiCkeD:包含失配的模拟电路合成
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852720
K. Antreich, Josef Eckmüller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala
{"title":"WiCkeD: analog circuit synthesis incorporating mismatch","authors":"K. Antreich, Josef Eckmüller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala","doi":"10.1109/CICC.2000.852720","DOIUrl":"https://doi.org/10.1109/CICC.2000.852720","url":null,"abstract":"This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"19 1","pages":"511-514"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84017351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A partitioned wavelet-based approach for image compression using FPGA's 基于FPGA的分割小波图像压缩方法
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852727
Joerg Ritter, P. Molitor
{"title":"A partitioned wavelet-based approach for image compression using FPGA's","authors":"Joerg Ritter, P. Molitor","doi":"10.1109/CICC.2000.852727","DOIUrl":"https://doi.org/10.1109/CICC.2000.852727","url":null,"abstract":"Discrete wavelet transformations (DWT) followed by embedded zerotree encoding (EZT) is a very efficient technique for image compression. However, the algorithms proposed in the literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we introduce efficient FPGA hardware approaches for DWT for lossless and lossy image compression targeting the minimization of external memory accesses. In particular, the approaches allow both parallel wavelet transformation and parallel embedded zero tree encoding.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"28 1","pages":"547-550"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89447400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Quantitative characterization of substrate noise for physical design guides in digital circuits 数字电路物理设计指南中衬底噪声的定量表征
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852626
M. Nagata, J. Nagai, T. Morie, A. Iwata
{"title":"Quantitative characterization of substrate noise for physical design guides in digital circuits","authors":"M. Nagata, J. Nagai, T. Morie, A. Iwata","doi":"10.1109/CICC.2000.852626","DOIUrl":"https://doi.org/10.1109/CICC.2000.852626","url":null,"abstract":"Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 /spl mu/V resolution. Activity in a digital block is a key parameter to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as ringing.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"48 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75958568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new design for complete on-chip ESD protection 全新设计的完整片上ESD保护
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852624
Albert Z. H. Wang
{"title":"A new design for complete on-chip ESD protection","authors":"Albert Z. H. Wang","doi":"10.1109/CICC.2000.852624","DOIUrl":"https://doi.org/10.1109/CICC.2000.852624","url":null,"abstract":"The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"22 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80242767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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