WiCkeD:包含失配的模拟电路合成

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852720

K. Antreich, Josef Eckmüller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala

{"title":"WiCkeD:包含失配的模拟电路合成","authors":"K. Antreich, Josef Eckmüller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala","doi":"10.1109/CICC.2000.852720","DOIUrl":null,"url":null,"abstract":"This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"19 1","pages":"511-514"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"WiCkeD: analog circuit synthesis incorporating mismatch\",\"authors\":\"K. Antreich, Josef Eckmüller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala\",\"doi\":\"10.1109/CICC.2000.852720\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"19 1\",\"pages\":\"511-514\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852720\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852720","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 36

摘要

本文提出了一种新的基于仿真的模拟合成工具WiCkeD中考虑局部过程变化的方法，这些变化对失匹配敏感的模拟组件有重要影响。WiCkeD包括公差分析、性能优化和设计定心，是工业中用于设计模拟CMOS电路的大学工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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WiCkeD: analog circuit synthesis incorporating mismatch

This paper presents a method to consider local process variations, which crucially influence the mismatch-sensitive analog components, within a new simulation-based analog synthesis tool called WiCkeD. WiCkeD includes tolerance analysis, performance optimization and design centering, and is a university tool used in industry for the design of analog CMOS circuits.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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