Analysis of jitter due to power-supply noise in phase-locked loops

P. Heydari, M. Pedram
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引用次数: 47

Abstract

Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 /spl mu/m CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model.
锁相环中电源噪声引起的抖动分析
锁相环(PLL)在射频和混合信号VLSI电路经历电源噪声转化为时序抖动。本文分析了由电源轨噪声引起的时序抖动问题。首先给出了不同片上去耦电容值下超大规模集成电路中电源噪声的随机模型。然后根据电源噪声的统计特性计算压控振荡器(VCO)的相位噪声。最后根据压控振荡器相位噪声预测锁相环的时序抖动。在0.35 /spl mu/m CMOS工艺下设计了锁相环电路,并应用数学模型确定了时序抖动。实验结果证明了预测模型的准确性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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