Ultra low-power CMOS IC using partially-depleted SOI technology

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852617

A. Ebina, T. Kadowaki, Y. Sato, M. Yamaguchi

引用次数: 8

Abstract

We have developed an ultra low power IC for wrist-watch application. The realized operation current and voltage were 30 nA and 0.42 V respectively. This extremely low power operation was achieved by taking full advantage of body-floated devices with the partially-depleted SOI CMOS technology.

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超低功耗CMOS集成电路采用部分耗尽SOI技术

我们开发了一种超低功耗的腕表集成电路。实现的工作电流为30 nA，工作电压为0.42 V。这种极低功耗的工作是通过充分利用体浮器件和部分耗尽的SOI CMOS技术实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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