全新设计的完整片上ESD保护

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852624

Albert Z. H. Wang

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引用次数: 6

摘要

报道了一种新型紧凑型静电放电(ESD)防护结构的设计。提供从I/O到电源V/sub DD/的正/负、从I/O到地、从V/sub DD/到地的正/负全方位ESD保护。这种超高速(t/sub 1//spl sim/0.16 nS)结构对称运行。测量显示低保持电压(/spl sim/2 V)，低放电阻抗(/spl sim//spl Omega/)和可调触发电压。ESD测试通过14 kV (HBM)。通过全面的ESD仿真实现了设计预测。它对射频集成电路特别好。

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A new design for complete on-chip ESD protection

The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground. This ultra-fast (t/sub 1//spl sim/0.16 nS) structure operates symmetrically. Measurements showed low holding voltage (/spl sim/2 V), low discharging impedance (/spl sim//spl Omega/), and adjustable triggering voltages. ESD tests passed 14 kV (HBM). Design prediction was achieved by comprehensive ESD simulation. It is particularly good for RF ICs.

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来源期刊

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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