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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)最新文献

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A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V 一个100 msps的8-b CMOS分位ADC，参数操作范围从3.8 V降至2.2 V
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852660
R. Taft, M. R. Tursi
{"title":"A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V","authors":"R. Taft, M. R. Tursi","doi":"10.1109/CICC.2000.852660","DOIUrl":"https://doi.org/10.1109/CICC.2000.852660","url":null,"abstract":"A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four circuit techniques: differential T-gate boosting, a unified coarse/fine analog channel with dual gain, a supply independent delay generator, and a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained down to 2.2 V, 84 mW.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"103 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75931702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design validation of .18 /spl mu/m 1 GHz cache and register arrays .18 /spl mu/m 1ghz高速缓存和寄存器阵列的设计验证
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852670
D. Malone, Paul Bunce, Joe DellaPietro, John Davis, J. Dawson, T. Knips, D. Plass, Phil Pritzlaff, Kenneth Reyer
{"title":"Design validation of .18 /spl mu/m 1 GHz cache and register arrays","authors":"D. Malone, Paul Bunce, Joe DellaPietro, John Davis, J. Dawson, T. Knips, D. Plass, Phil Pritzlaff, Kenneth Reyer","doi":"10.1109/CICC.2000.852670","DOIUrl":"https://doi.org/10.1109/CICC.2000.852670","url":null,"abstract":"This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"57 1","pages":"295-298"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77762789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wire planning for performance and yield enhancement 线材规划，以提高性能和良率
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852629
C. Ouyang, Kyungsuk Ryu, H. Heineken, Jitu Khare, S. Shaikh, M. d'Abreu
{"title":"Wire planning for performance and yield enhancement","authors":"C. Ouyang, Kyungsuk Ryu, H. Heineken, Jitu Khare, S. Shaikh, M. d'Abreu","doi":"10.1109/CICC.2000.852629","DOIUrl":"https://doi.org/10.1109/CICC.2000.852629","url":null,"abstract":"In this paper, a wire planning strategy at the layout stage is proposed. The strategy addresses deep sub-micron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitivity to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"61 1","pages":"113-116"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86004330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel high-performance predictable circuit architecture for the deep sub-micron era 深亚微米时代一种新颖的高性能可预测电路架构
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852718
Yonghee Im, K. Roy
{"title":"A novel high-performance predictable circuit architecture for the deep sub-micron era","authors":"Yonghee Im, K. Roy","doi":"10.1109/CICC.2000.852718","DOIUrl":"https://doi.org/10.1109/CICC.2000.852718","url":null,"abstract":"Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger interwire capacitance which is responsible for large crosstalk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O/sup 2/ABA), especially suited for the deep sub-micron regime. O/sup 2/ABA achieves reduction of crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O/sup 2/ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"26 1","pages":"503-506"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78089551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A stand-alone integrated excitation/extraction system for analog BIST applications 一个独立的集成励磁/提取系统模拟BIST应用
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852623
M. Hafed, G. Roberts
{"title":"A stand-alone integrated excitation/extraction system for analog BIST applications","authors":"M. Hafed, G. Roberts","doi":"10.1109/CICC.2000.852623","DOIUrl":"https://doi.org/10.1109/CICC.2000.852623","url":null,"abstract":"An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"10 1","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79202249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA 解决可重构FPGA可满足性问题的并行和可扩展架构
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852637
Tarachand Pagarani, F. Kocan, D. Saab, J. Abraham
{"title":"Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA","authors":"Tarachand Pagarani, F. Kocan, D. Saab, J. Abraham","doi":"10.1109/CICC.2000.852637","DOIUrl":"https://doi.org/10.1109/CICC.2000.852637","url":null,"abstract":"In this paper, we present different architectures and implementation for solving the general SATisfiability (SAT) problem on reconfigurable devices. In particular, we address the solution of this basic and important problem using multiple small FPGAs. Our approach utilizes partitioning and decomposition to map any large SAT problem on more than one small FPGA. First, a SAT problem is decomposed into several independent sub-problems. This way, all sub-problems may be solved on different FPGAs simultaneously. If any of the sub-problems can not fit on a single FPGA, then a second technique is used to divide the sub-problem into dependent parts. We compute the solution time and hardware resources for both approaches and also compare our results with the previously published results.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"56 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87836098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An analog front-end LSI with on-chip isolator for V.90 56 kbps modems 具有片上隔离器的模拟前端LSI，适用于V.90 56 kbps调制解调器
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852678
N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, Kazuhisa Takami, Y. Takeuchi, Atsuko Yano, Yasuo Shima
{"title":"An analog front-end LSI with on-chip isolator for V.90 56 kbps modems","authors":"N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, Kazuhisa Takami, Y. Takeuchi, Atsuko Yano, Yasuo Shima","doi":"10.1109/CICC.2000.852678","DOIUrl":"https://doi.org/10.1109/CICC.2000.852678","url":null,"abstract":"This paper presents an isolated analog front-end (I-AFE) LSI with built-in isolation function for V.90, 56 kbps modems. The LSI has 1.5 kVrms. AC isolation and analog front-end functions within a 5 mm/spl times/4.5 mm die with 0.4 /spl mu/m SOI CMOS process and a 50 pin TSOP package. The on-chip isolation approach eliminates external isolation devices such as transformers or photo-couplers. A 100 Mbps transmission rate is attained by the on-chip isolator.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"60 1","pages":"327-330"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82341058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process 在0.5-/spl mu/m CMOS工艺中实现的插入损耗为0.8 db的900 mhz T/R开关
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852680
F. Huang, K. O. Kenneth
{"title":"A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process","authors":"F. Huang, K. O. Kenneth","doi":"10.1109/CICC.2000.852680","DOIUrl":"https://doi.org/10.1109/CICC.2000.852680","url":null,"abstract":"A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"78 1","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82362301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Firm IP development: methodology and deliverables 公司知识产权开发:方法论和可交付成果
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852723
A. Ranjit, P. Ramkumar, V. Noel
{"title":"Firm IP development: methodology and deliverables","authors":"A. Ranjit, P. Ramkumar, V. Noel","doi":"10.1109/CICC.2000.852723","DOIUrl":"https://doi.org/10.1109/CICC.2000.852723","url":null,"abstract":"This paper addresses the need to develop firm intellectual properties (IPs) with a standard set of deliverables so they can be integrated with very little effort. We have presented the design flow used for developing a firm IP. A DMA controller is used as an example. The paper highlights the deliverables from a IP vendor/user perspective to proliferate the acceptance and usage of the IP.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"80 1","pages":"529-532"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83846464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-thread VLIW processor architecture for HDTV decoding 用于HDTV解码的多线程VLIW处理器架构
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852730
Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, I. Park
{"title":"Multi-thread VLIW processor architecture for HDTV decoding","authors":"Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, I. Park","doi":"10.1109/CICC.2000.852730","DOIUrl":"https://doi.org/10.1109/CICC.2000.852730","url":null,"abstract":"This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"16 1","pages":"559-562"},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77486072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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