Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA

Tarachand Pagarani, F. Kocan, D. Saab, J. Abraham
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引用次数: 11

Abstract

In this paper, we present different architectures and implementation for solving the general SATisfiability (SAT) problem on reconfigurable devices. In particular, we address the solution of this basic and important problem using multiple small FPGAs. Our approach utilizes partitioning and decomposition to map any large SAT problem on more than one small FPGA. First, a SAT problem is decomposed into several independent sub-problems. This way, all sub-problems may be solved on different FPGAs simultaneously. If any of the sub-problems can not fit on a single FPGA, then a second technique is used to divide the sub-problem into dependent parts. We compute the solution time and hardware resources for both approaches and also compare our results with the previously published results.
解决可重构FPGA可满足性问题的并行和可扩展架构
在本文中,我们提出了不同的架构和实现来解决可重构器件的一般可满足性(SAT)问题。特别是,我们使用多个小型fpga来解决这个基本而重要的问题。我们的方法利用分区和分解将任何大型SAT问题映射到多个小型FPGA上。首先,将SAT问题分解为几个独立的子问题。这样,所有子问题可以同时在不同的fpga上解决。如果任何子问题不能在单个FPGA上容纳,则使用第二种技术将子问题划分为相关的部分。我们计算了两种方法的解决时间和硬件资源,并将我们的结果与之前发表的结果进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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