线材规划,以提高性能和良率

C. Ouyang, Kyungsuk Ryu, H. Heineken, Jitu Khare, S. Shaikh, M. d'Abreu
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引用次数: 4

摘要

本文提出了一种布线阶段的线材规划策略。该策略解决了设计师和制造工程师面临的深亚微米(DSM)问题。对于设计人员来说,所提出的方法降低了交叉耦合电容的大小和方差,使互连延迟更小,更可预测。对于制造工程师来说,该方法降低了对随机缺陷和工艺变化的设计敏感性,从而提高了良率。这些目标是通过指导商业定位和路由工具在整个模具上更均匀地利用路由资源来实现的。给出了线路规划策略的示例实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Wire planning for performance and yield enhancement
In this paper, a wire planning strategy at the layout stage is proposed. The strategy addresses deep sub-micron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitivity to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.
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