一个100 msps的8-b CMOS分位ADC，参数操作范围从3.8 V降至2.2 V

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852660

R. Taft, M. R. Tursi

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引用次数: 4

摘要

一个100 msps的8位ADC通过四种电路技术获得非常低的电源电压工作:差分t门升压，具有双增益的统一粗/细模拟通道，电源无关延迟发生器和延时锁环数字输出驱动器。最大DNL低于0.5 LSB和7.0(7.3)有效位，50 MHz (10 MHz)输入保持低至2.2 V, 84 mW。

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A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V

A 100-MSPS 8-bit ADC obtains very low supply voltage operation with four circuit techniques: differential T-gate boosting, a unified coarse/fine analog channel with dual gain, a supply independent delay generator, and a delay-lock loop digital output driver. A maximum DNL below 0.5 LSB and 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained down to 2.2 V, 84 mW.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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