{"title":"在0.5-/spl mu/m CMOS工艺中实现的插入损耗为0.8 db的900 mhz T/R开关","authors":"F. Huang, K. O. Kenneth","doi":"10.1109/CICC.2000.852680","DOIUrl":null,"url":null,"abstract":"A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"78 1","pages":"341-344"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process\",\"authors\":\"F. Huang, K. O. Kenneth\",\"doi\":\"10.1109/CICC.2000.852680\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"78 1\",\"pages\":\"341-344\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852680\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-/spl mu/m CMOS process
A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-dB insertion loss and a 17-dBm P/sub 1dB/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 dB compression point is achieved by DC biasing the input and output nodes.