.18 /spl mu/m 1ghz高速缓存和寄存器阵列的设计验证

D. Malone, Paul Bunce, Joe DellaPietro, John Davis, J. Dawson, T. Knips, D. Plass, Phil Pritzlaff, Kenneth Reyer
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引用次数: 1

摘要

本文介绍了在IBM .18 /spl mu/m 7级金属铜技术下的SRAM原型测试芯片的设计和实验结果。将讨论确保产品在宽工艺范围内的1ghz应用的结果和方法。IBM S/390 L2高速缓存芯片的积极产品周期时间SRAM应用需要多方面的方法来解决以下问题:(a) SRAM在类产品时钟和ABIST环境中的可操作性,(b)使用二维冗余演示产量,(c)宏观定时规则中使用的SRAM信号表征,(d)获得大批量的产品前制造测试数据,(e)在技术压力测试条件下验证SRAM功能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design validation of .18 /spl mu/m 1 GHz cache and register arrays
This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (a) SRAM operability in product-like clocking and ABIST environments, (b) Demonstration of yield using 2 dimensional redundancy, (c) Characterization of SRAM signals used in the macro timing rules, (d) Obtain high volume pre-product manufacturing test data, (e) Verify SRAM functionality at technology stress test conditions.
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