数字电路物理设计指南中衬底噪声的定量表征

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852626

M. Nagata, J. Nagai, T. Morie, A. Iwata

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引用次数: 2

摘要

基片噪声通过增益校准的基片电压测量，在100 ps-100 /spl mu/V分辨率下进行定量评估。数字块中的活度是噪声强度与之成正比的关键参数，降低活度是抑制噪声的直接而通用的方法。在源电路中使用开尔文接地，并在靠近接收电路的地方放置一个保护带，也可以显著地减弱噪声，然而，这种效果仅限于低频成分，如振铃。

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Quantitative characterization of substrate noise for physical design guides in digital circuits

Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 /spl mu/V resolution. Activity in a digital block is a key parameter to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as ringing.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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