MOS transistor modeling for RF integrated circuit design

The design of radio-frequency (RF) integrated circuits in deep-submicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and even beyond. Unfortunately, the currently available compact models give inaccurate results if they are not modified adequately. This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical and scalable equivalent circuit that can easily be implemented as a Spice subcircuit is described. The small-signal, noise and large-signal operations are discussed and measurements made on a 0.25 /spl mu/m CMOS process are presented that validate the RF MOS model up to 10 GHz.