一种用于5 mcps DS-CDMA解调器的2 v 3.7 mw延迟锁相环，采用循环积分器相关器

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852613

Y. Fujimoto, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz

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引用次数: 1

摘要

针对IMT-2000的5 mcps DS-CDMA解调器的延迟锁环(DLL)已经实现，由六个相关器组成，每个相关器都包含一种称为回收积分器的/spl Delta//spl Sigma/调制形式，以获得接收信号和PN序列之间的量化相关值。DLL可以适应从32到256的扩频比，当扩频比较小时，通过一个辅助ADC弥补动态范围退化。该芯片采用0.35-/spl mu/m双金属双聚CMOS工艺制造，芯片占地2.28 mm/sup 2/，在2 V电源电压下功耗3.7 mW。

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A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator

A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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