Architecture of cluster-based FPGAs with memory

Abstract

Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.