CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

David J. Foley, M. Flynn
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引用次数: 141

Abstract

This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.
基于2v, 3.2 ps抖动,1ghz时钟合成器和温度补偿可调振荡器的CMOS DLL
本文介绍了一种低电压、低抖动时钟合成器和温度补偿可调谐振荡器。这两种电路都采用自校正延迟锁相环(DLL)。DLL提供多个时钟相位,这些相位组合起来为合成器产生所需的输出频率,并为可调谐振荡器提供温度补偿偏置。在2v电源下,1 GHz合成器输出的RMS抖动为3.2 ps。在3.3 V电源下,1.6 GHz合成器输出的RMS抖动为3.1 ps。可调谐振荡器在环境温度范围从0到85/spl度/C有1.8%的频率变化。电路采用通用的0.5 /spl mu/m数字CMOS工艺制作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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