媒体处理器核心架构为实时、双向MPEG4/H。26X编解码器，30帧/秒的cif视频

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852711

T. Kamemaru, H. Ohira, H. Suzuki, K. Asano, M. Yoshimoto, Tokumichi Murakami

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引用次数: 6

摘要

我们开发了一个MPEG4/H媒体处理器核心。26X编解码LSI，实现了对帧率为30帧/秒的cif分辨率视频的实时双向编解码。核心处理器包含6.3个m -晶体管，仅在14毫米的硅面积上，功耗为280兆瓦，电压为1.8 V。它具有面向mpeg的混合架构，其中包含针对矩阵操作优化的SIMD处理器，可编程VLC引擎和二维多功能DMA。另一个特点是硬件辅助的内存减少方法和操作数隔离方案，分别实现了低成本和低功耗特性。

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Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video

We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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