Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

A scalable curve-fit model of the substrate coupling resistances for IC design 集成电路设计中衬底耦合电阻的可扩展曲线拟合模型

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187517

V. Gurugubelli, S. Karmalkar

引用次数: 2

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application 用于单端口SRAM的准平面三栅极(QPT)体CMOS技术

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187505

Y. Tsukamoto, M. Yabuuchi, H. Fujiwara, K. Nii, C. Shin, T. Liu

引用次数: 0

Vertical Slit Field Effect Transistor in ultra-low power applications 超低功耗应用中的垂直狭缝场效应晶体管

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187522

Xiang Qiu, M. Marek-Sadowska, W. Maly

引用次数: 10

An area efficient on-chip hybrid voltage regulator 一种面积高效的片上混合稳压器

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187524

Selçuk Köse, E. Friedman, S. Tarn, Sally Pinzon, B. McDermott

引用次数: 23

Optimal microarchitectural design configuration selection for processor hard-error reliability 处理器硬错误可靠性的最优微架构设计配置选择

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187479

Ying Zhang, Lide Duan, Bin Li, Lu Peng

引用次数: 2

Functional test pattern generation for maximizing temperature in 3D IC chip stack 三维集成电路芯片堆中温度最大化的功能测试图生成

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187482

S. Srinivasan, S. Kundu

{"title":"Functional test pattern generation for maximizing temperature in 3D IC chip stack","authors":"S. Srinivasan, S. Kundu","doi":"10.1109/ISQED.2012.6187482","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187482","url":null,"abstract":"In a stacked 3D Integrated Circuit (IC), the total power dissipated per unit surface area typically exceeds that of 2D ICs. This results in creation of a greater number of localized thermal hotspots in individual dies of the 3D IC. The location and temperature of these hotspots depend on the actual workload executing on a 3D IC. Since the power dissipation pattern from the applied workload may vary over time, the location and intensity of thermal hotspots may vary with it. The applied workload may be construed as consisting of phases, where the spatial power dissipation pattern remains constant over a phase and changes only from one phase to another. In this paper (i) we develop a thermal modeling scheme that predicts temperature profile at the end of a program phase, and use (ii) a novel Integer Linear Programming (ILP) formulation to arrange program phases to create worst case temperature at a target location. Experimental results show that, by taking the spatio-temporal effect into account, we can raise temperature of a hotspot much higher than what is possible from purely functional trace. Hotspot temperature maximization is important in design verification and testing.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Process variation aware DRAM design using block based adaptive body biasing algorithm 基于分块自适应体偏置算法的过程变化感知DRAM设计

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187503

S. Desai, Sanghamitra Roy, Koushik Chakraborty

{"title":"Process variation aware DRAM design using block based adaptive body biasing algorithm","authors":"S. Desai, Sanghamitra Roy, Koushik Chakraborty","doi":"10.1109/ISQED.2012.6187503","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187503","url":null,"abstract":"Large dense structures like DRAMs are particularly susceptible to process variation, which can lead to variable latencies in different memory arrays. However, very little work exists on variation studies in the DRAM. This is due to the fact that DRAMs were traditionally placed off-chip and their latency changes due to process variation did not impact the overall processor performance. However, emerging technology trends like three dimensional integration, use of sophisticated memory controllers and continued scaling of technology nodes, substantially reduces DRAM access latency. Hence future technology nodes will see widespread adoption of embedded DRAMs. This makes process variation a critical upcoming challenge in DRAMs that must be addressed in current and forthcoming technology generations. In this paper, we present techniques for modeling the effect of random as well as spatial variation in large DRAM array structures. We use sensitivity based gate level process variation models combined with statistical timing analysis to estimate the impact of process variation on the DRAM performance and leakage power. We also propose a simulated annealing based Vth assignment algorithm using adaptive body biasing to improve the yield of DRAM structures. Applying our algorithm on a 1GB DRAM array, we report an average of 10.3% improvement in the DRAM yield. To the best of our knowledge, ours is the first technique to model the impact of process variation on large scale DRAM arrays.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability 一种新的样品重用方法，用于制造变异性的快速统计模拟

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187564

R. Kanj, R. Joshi

引用次数: 2

Impact of C-elements in asynchronous circuits c元在异步电路中的影响

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187530

Matheus T. Moreira, B. Oliveira, F. Moraes, Ney Laert Vilar Calazans

引用次数: 36

VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS VAR-TX:一种可变感知SRAM模型，用于预测最佳架构，以实现在纳米级CMOS中提高良率的最小访问时间

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187541

Jeren Samandari-Rad, Matthew R. Guthaus, R. Hughey

{"title":"VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS","authors":"Jeren Samandari-Rad, Matthew R. Guthaus, R. Hughey","doi":"10.1109/ISQED.2012.6187541","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187541","url":null,"abstract":"In this paper we propose a new hybrid analytical-empirical model, called VAR-TX, that exhaustively computes and compares all feasible architectures subject to inter-die (DID) and intra-die (WID) process variations (PV). Based on its computation, VAR-TX predicts the optimal architecture that provides minimum access-time and minimum access-time variation for yield enhancement in future 16-nm on-chip conventional six-transistor static random access memories (6T-SRAMs) of given input specifications. These specifications include SRAM size and shape, number of columns, and word-size. We compare the impact of D2D and WID variations on access-time for 16-nm SRAM with the 45-nm and 180-nm nodes and demonstrate that the drastic increase in the 1- and 3-sigma of the smaller nodes is mainly due to the increase in the WID variations. Finally, our model disputes previously published works-suggesting that square SRAM always produces minimum delays-and significantly extends and enhances the older models by adding both an extra dimension of architectural consideration and additional device parameter fluctuation to the analysis, while producing delay estimates within 4% of Hspice results.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121038922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8