Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献_第10页

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs) 基于体电压传感的自旋转矩传递RAMs (STT-RAMs)短脉冲读取电路

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187506

Fengbo Ren, Henry Park, R. Dorrance, Y. Toriyama, C. Yang, D. Markovic

{"title":"A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)","authors":"Fengbo Ren, Henry Park, R. Dorrance, Y. Toriyama, C. Yang, D. Markovic","doi":"10.1109/ISQED.2012.6187506","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187506","url":null,"abstract":"With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte-Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 ft in the nominal case.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128431044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method 基于不连续Galerkin有限元法的三维集成电路热分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187483

A. Zjajo, N. V. D. Meijs, R. V. Leuken

引用次数: 11

Speed-path analysis for multi-path failed latches with random variation 随机变化多路径失效锁存器的速度路径分析

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187547

Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, H. Komatsu

{"title":"Speed-path analysis for multi-path failed latches with random variation","authors":"Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, H. Komatsu","doi":"10.1109/ISQED.2012.6187547","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187547","url":null,"abstract":"In processor and high-end chip designs, path delay difference between pre-silicon and post-silicon have become an important issue. Identifying the factors for the difference with speed limiting paths is required to achieve target performance. A statistical diagnosis framework, called speed-path analysis, identifies them. Speed-path analysis uses fail data from at-speed delay test with silicon samples. Since at-speed delay test activates multiple paths simultaneously, it makes many failed latches with multiple sensitized paths. We will refer to these failed latches as multi-path failed latches. Previous works have not discussed how to handle multi-path failed latches because they are discussions under the assumption that path delay differences are obtained correctly. Generating additional test patterns to activate a single path for each latch is a very time-consuming task. Without using multi-path failed latches from at-speed delay test, the fatal factors for path delay differences with speed limiting paths can be missed because the number of non multi-path failed latches is small. This paper proposes methods for handling multi-path failed latches. By experiments based on a test processor design, we can deal with 12% of the timing-critical latches adopted as failed latches while 1% using only non multi-path failed latches.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124443996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Device- and system-level performance modeling for graphene P-N junction logic 石墨烯P-N结逻辑的器件和系统级性能建模

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187504

C. Pan, A. Naeemi

{"title":"Device- and system-level performance modeling for graphene P-N junction logic","authors":"C. Pan, A. Naeemi","doi":"10.1109/ISQED.2012.6187504","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187504","url":null,"abstract":"Based on the property of angular dependent transmission probability of electrons observed in graphene PN junctions, a modified MUX-based graphene logic device is introduced. A more elaborate resistance model including ON resistance, leakage resistance and contact resistance is given as well as a capacitance model of the device. Compared with Si CMOS switches, MUX-based logic graphene gates have potentially lower output resistances and a smaller device area. Since interconnects play an ever increasing important role in digital circuit, for the first time, module-level and system-level analyses are made for better evaluating the potential performance of graphene logic devices. Based on the analysis of a 32-bit Han-Carlson adder, module-level evaluation has been done and comparison has been made between graphene logic circuits complemented by multilayer graphene interconnects and CMOS logic circuits with Cu/low k interconnects. The results indicate that MUX-based graphene logic circuits can outperform CMOS circuits in terms of both delay and power consumption. Both devices being evaluated are based on the 15nm technology node. For the system-level analysis, the graphene logic system can have 50% higher throughput than its Si CMOS counterpart with the same power density and die size area.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A new voltage binning technique for yield improvement based on graph theory 一种基于图论的提高成品率的电压分组新技术

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187501

Ruijing Shen, S. Tan, Xuexin Liu

{"title":"A new voltage binning technique for yield improvement based on graph theory","authors":"Ruijing Shen, S. Tan, Xuexin Liu","doi":"10.1109/ISQED.2012.6187501","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187501","url":null,"abstract":"In this paper, we propose a new voltage binning technique to improve yield. Voltage binning technique tries to assign different supply voltages to different chips in order to improve the yield. A novel valid voltage segment concept is proposed, which is determined by the timing and power constraints of chips. Then we develop a formulation to predict the maximum number of bins required under the uniform binning scheme from the distribution of length of valid supply voltage segment. With the new concept, an optimal binning scheme can be modeled as a set-cover problem. A greedy algorithm is developed to solve the set-cover problem in an incremental way. The new method is also extendable to deal with a range of working supply voltages for dynamic voltage scaling under different operation modes (like lower power and high performance modes). Experimental results on some benchmarks in 45nm technology show that the proposed method can correctly predict the upper bound on the number of bins required. The optimal binning scheme can lead to significant saving for the number of bins compared to the uniform one to achieve the same yield with very small CPU cost.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design of an efficient NoC architecture using millimeter-wave wireless links 采用毫米波无线链路的高效NoC架构设计

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187490

Sujay Deb, Kevin Chang, A. Ganguly, Xinmin Yu, C. Teuscher, P. Pande, D. Heo, B. Belzer

引用次数: 37

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop 高可靠的SEU硬化锁存器和高性能SEU硬化触发器

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187516

Riadul Islam

{"title":"A highly reliable SEU hardened latch and high performance SEU hardened flip-flop","authors":"Riadul Islam","doi":"10.1109/ISQED.2012.6187516","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187516","url":null,"abstract":"In this paper, we present a novel single event upset (SEU) hardened latch. The latch consists of a new 12 transistor (12T) SEU hardened storage cell and a C-element. It is insensitive to single event transient (SET) affecting it's internal and output nodes. The differential writing capability of the proposed storage cell is very attractive for designing flip-flops. In addition, we present a high performance SEU hardened D type edge triggered flip-flop, particularly attractive for low data switching activity. The flip-flop utilizes an output feedback connection to the input register stage, in order to reduce power consumption at low data switching activity and eliminate the hold time constraint from traditional clocked CMOS register. We have implemented the proposed latch and the flip-flop in a standard 65 nm CMOS technology. We have investigated power consumptions, propagation delay, SET sensitivity and the area penalty of the proposed latch and flip-flop comparing with the recently reported SEU hardened latches and flip-flops. The proposed latch exhibits as much as 17% lower power-delay product (PDP) compared to recently reported SEU hardened latch, and the proposed flip-flop exhibits lower or comparable PDP compared to recently reported SEU hardened flip-flop while offering more robustness to particle induced SET.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix TSV的器件和电磁联合仿真:衬底噪声研究和矩阵中TSV的紧凑建模

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187525

P. L. Maitre, M. Brocard, A. Farcy, J. Marin

引用次数: 2

Assertion clustering for compacted test sequence generation 用于压缩测试序列生成的断言聚类

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187567

J. G. Tong, Marc Bottle, Z. Zilic

引用次数: 8

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects 基于布局相关效应的几何规划模型的CMOS运算放大器电路合成

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187534

Yu Zhang, Bo Liu, Bo Yang, Jing Li, S. Nakatake

引用次数: 15