Thirteenth International Symposium on Quality Electronic Design (ISQED)最新文献

A variation and energy aware ILP formulation for task scheduling in MPSoC MPSoC中任务调度的可变和能量感知ILP公式

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-04-19 DOI: 10.1109/ISQED.2012.6187578

Mahboobeh Ghorbani

引用次数: 10

Automated correction of design errors by edge redirection on High-Level Decision Diagrams 在高级决策图上通过边缘重定向自动纠正设计错误

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-04-19 DOI: 10.1109/ISQED.2012.6187566

Anton Karputkin, R. Ubar, M. Tombak, J. Raik

引用次数: 3

Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process 动态偏置低功耗高性能3.3V输出缓冲器，单孔体CMOS 1.8V氧化物45nm工艺

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187489

K. Rajagopal

引用次数: 1

Effcient approaches to overcome non-convexity issues in analog design automation 模拟设计自动化中克服非凸性问题的有效方法

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187550

S. Maji, P. Mandal

引用次数: 7

Functional composition: A new paradigm for performing logic synthesis 功能组合:执行逻辑综合的新范例

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187500

Mayler G. A. Martins, Renato P. Ribas, A. Reis

引用次数: 23

Hot peripheral thermal management to mitigate cache temperature variation 热外围热管理，以减轻缓存温度变化

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187576

H. Homayoun, M. Rahmatian, Vasileios Kontorinis, Shahin Golshan, D. Tullsen

引用次数: 12

Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization 普通Kriging元模型辅助蚁群算法快速模拟设计优化

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187533

Oghenekarho Okobiah, S. Mohanty, E. Kougianos

{"title":"Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos","doi":"10.1109/ISQED.2012.6187533","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187533","url":null,"abstract":"This paper explores an ordinary Kriging based metamodeling technique that allows designers to create a model of a circuit with very good accuracy, while greatly reducing the time required for simulations. Regression and interpolation based methods have been researched extensively and are a commonly used technique for creating metamodels. However, they do not take into account the effect of correlation between design and process parameters, which are critical in the nanoscale regime. Kriging provides an improved metamodeling technique which takes into effect correlation effects during the metamodel generation phase. The ordinary Kriging metamodels are subjected to an Ant Colony Optimization (ACO) algorithm that enables fast optimization of the circuit. This design methodology is evaluated on a sense amplifier circuit as a case study. The results show that the Kriging based metamodels are very accurate and the ACO based algorithm optimizes the sense amplifier precharge time with power consumption as a design constraint in an average time of 3.7 minutes (optimization on the metamodel), compared to 72 hours (optimization on the SPICE netlist).","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128504779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices 采用纳米级tsv和器件构建的3D集成电路的设计质量权衡研究

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187574

Kaiyuan Yang, Daehyun Kim, S. Lim

引用次数: 12

Efficient reduction techniques for statistical model generation of standard cells 标准细胞统计模型生成的高效约简技术

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187518

Sachin Shrivastava, H. Parameswaran

引用次数: 0

Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit 利用施密特触发器(FEST)电路的反馈均衡降低数字逻辑中的误差

Thirteenth International Symposium on Quality Electronic Design (ISQED) Pub Date : 2012-03-19 DOI: 10.1109/ISQED.2012.6187511

Zafar Takhirov, B. Nazer, A. Joshi

{"title":"Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit","authors":"Zafar Takhirov, B. Nazer, A. Joshi","doi":"10.1109/ISQED.2012.6187511","DOIUrl":"https://doi.org/10.1109/ISQED.2012.6187511","url":null,"abstract":"Voltage scaling is commonly used to reduce the energy consumption of digital CMOS logic. However, as the supply voltage decreases, transistor switching times increase, leading to intersymbol interference (ISI) between successive outputs of the digital logic. This limits the amount of voltage scaling that can be applied for a target performance. We describe a novel circuit-level technique that couples feedback equalization with a Schmitt trigger (FEST) to suppress this ISI, which in turn enables further voltage scaling while ensuring reliable operation at the desired target performance. For a 4-bit, 22 nm Kogge-Stone adder designed for 2 GHz operation, the proposed technique lowers the critical voltage (beyond which frequent timing errors occur) from 580 mV (nominal design) to 510 mV (design with FEST circuit), providing a 20% decrease in energy per operation. We also apply this technique to a 3-tap 4-bit finite impulse response (FIR) filter operating at 500 MHz, and observe that the critical voltage drops from 680 mV (nominal design) to 510 mV (design with FEST circuit) and the energy per operation can be decreased by up to 40%.","PeriodicalId":205874,"journal":{"name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133986029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17