Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit

Abstract

Voltage scaling is commonly used to reduce the energy consumption of digital CMOS logic. However, as the supply voltage decreases, transistor switching times increase, leading to intersymbol interference (ISI) between successive outputs of the digital logic. This limits the amount of voltage scaling that can be applied for a target performance. We describe a novel circuit-level technique that couples feedback equalization with a Schmitt trigger (FEST) to suppress this ISI, which in turn enables further voltage scaling while ensuring reliable operation at the desired target performance. For a 4-bit, 22 nm Kogge-Stone adder designed for 2 GHz operation, the proposed technique lowers the critical voltage (beyond which frequent timing errors occur) from 580 mV (nominal design) to 510 mV (design with FEST circuit), providing a 20% decrease in energy per operation. We also apply this technique to a 3-tap 4-bit finite impulse response (FIR) filter operating at 500 MHz, and observe that the critical voltage drops from 680 mV (nominal design) to 510 mV (design with FEST circuit) and the energy per operation can be decreased by up to 40%.